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224 条记录 (耗时 0.018 秒)

    Forming patterned graphene layers
    1.
    发明授权
    Forming patterned graphene layers 有权
    形成图案化石墨烯层

    公开(公告)号：US09102118B2

    公开(公告)日：2015-08-11

    申请号：US13310885

    申请日：2011-12-05

    申请人： Ali Afzali-Ardakani ,  Ahmed Maarouf ,  Glenn J. Martyna ,  Katherine Saenger

    发明人： Ali Afzali-Ardakani ,  Ahmed Maarouf ,  Glenn J. Martyna ,  Katherine Saenger

    IPC分类号： B82Y30/00 ,  B82Y40/00 ,  B32B3/00 ,  C01B31/02 ,  C23F1/02 ,  H01B13/00 ,  C01B31/04

    CPC分类号： H01B1/04 ,  B32B3/00 ,  B32B3/12 ,  B32B9/007 ,  B32B9/041 ,  B32B15/20 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2457/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C23F1/02 ,  H01L21/02527 ,  H01L21/042 ,  H01L21/324 ,  Y10T428/24545 ,  Y10T428/24851 ,  Y10T428/24909 ,  Y10T428/24917

    摘要： An apparatus and method for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure of a carbide-forming metal or metal-containing alloy on a substrate, applying a layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy on the substrate, heating the layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy in an environment to remove graphene regions proximate to the at least one patterned structure of a carbide-forming metal or metal-containing alloy, and removing the at least one patterned structure of a carbide-forming metal or metal-containing alloy to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices.

    摘要翻译： 一种用于在衬底上形成图案化的石墨烯层的装置和方法。 一种这样的方法包括在基底上形成碳化物形成金属或含金属合金的至少一个图案化结构，在碳化物形成金属或含金属合金的至少一个图案化结构的顶部上施加石墨烯层 在基板上，在环境中在形成碳化物的金属或含金属的合金的至少一个图案化结构的顶部上加热石墨烯层，以去除邻近碳化物形成金属的至少一个图案化结构的石墨烯区域 或含金属的合金，以及去除形成碳化物的金属或含金属的合金的至少一个图案化结构，以在衬底上产生图案化的石墨烯层，其中衬底上的图案化石墨烯层提供电子器件的载流子迁移率。

    Chemical oxidation of graphene and carbon nanotubes using Cerium (IV) ammonium nitrate
    3.
    发明授权
    Chemical oxidation of graphene and carbon nanotubes using Cerium (IV) ammonium nitrate 有权
    使用硝酸铈（IV）硝酸铵对石墨烯和碳纳米管进行化学氧化

    公开(公告)号：US08912525B2

    公开(公告)日：2014-12-16

    申请号：US13329115

    申请日：2011-12-16

    申请人： Ali Afzali-Ardakani ,  Bhupesh Chandra ,  George S. Tulevski

    发明人： Ali Afzali-Ardakani ,  Bhupesh Chandra ,  George S. Tulevski

    IPC分类号： H01L29/06

    CPC分类号： H01L29/78 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/168 ,  C01B32/194

    摘要： A process comprises combining a Ce (IV) salt with a carbon material comprising CNT or graphene wherein the Ce (IV) salt is selected from a Ce (IV) ammonium salt of a nitrogen oxide acid and is dissolved in a solvent comprising water. The process is conducted under conditions to substantially oxidize the carbon material to produce an oxidized material that is substantially non-conducting. After the oxidation, the Ce (IV) is substantially removed from the oxidized material. This produces a product made by the process. An article of manufacture comprises the product on a substrate. The oxidized material can be formed as a pattern on the substrate. In another embodiment the substrate comprises an electronic device with the oxidized material patterning non-conductive areas separate from conductive areas of the non-oxidized carbon material, where the conductive areas are operatively associated with the device.

    摘要翻译： 一种方法包括将Ce（IV）盐与包含CNT或石墨烯的碳材料组合，其中Ce（IV）盐选自氮氧化物的Ce（IV）铵盐，并溶解在包含水的溶剂中。 该方法在基本上氧化碳材料以产生基本不导电的氧化材料的条件下进行。 在氧化之后，Ce（IV）从氧化物质中大体上去除。 这产生了由该过程制成的产品。 制品包括在基材上的产品。 氧化物可以形成为基板上的图案。 在另一个实施例中，衬底包括电子器件，其中氧化材料图案化非导电区域与非氧化碳材料的导电区域分离，其中导电区域与器件可操作地相关联。

    Graphene transistors with self-aligned gates
    4.
    发明授权
    Graphene transistors with self-aligned gates 有权
    具有自对准栅极的石墨烯晶体管

    公开(公告)号：US08803130B2

    公开(公告)日：2014-08-12

    申请号：US13492097

    申请日：2012-06-08

    申请人： Ali Afzali-Ardakani ,  Phaedon Avouris ,  Damon B. Farmer ,  Yu-Ming Lin ,  Yu Zhu

    发明人： Ali Afzali-Ardakani ,  Phaedon Avouris ,  Damon B. Farmer ,  Yu-Ming Lin ,  Yu Zhu

    IPC分类号： H01L29/06

    CPC分类号： H01L29/1606 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/7781 ,  Y10S977/734

    摘要： Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.

    摘要翻译： 公开了石墨烯晶体管器件及其制造方法。 一种这样的石墨烯晶体管器件包括源电极和漏电极以及包括设置在源极和漏极之间的电介质侧壁间隔物的栅极结构。 该器件还包括与源极和漏极电极中的至少一个相邻的石墨烯层，其中源/漏电极和石墨烯层之间的界面在整个界面处保持一致的电导率。

    Vapor phase deposition processes for doping silicon
    8.
    发明授权
    Vapor phase deposition processes for doping silicon 失效
    掺杂硅的气相沉积工艺

    公开(公告)号：US08691675B2

    公开(公告)日：2014-04-08

    申请号：US12625835

    申请日：2009-11-25

    申请人： Ali Afzali-Ardakani ,  Damon B. Farmer ,  Lidija Sekaric

    发明人： Ali Afzali-Ardakani ,  Damon B. Farmer ,  Lidija Sekaric

    IPC分类号： H01L21/04

    CPC分类号： H01L21/2254

    摘要： A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

    摘要翻译： 用掺杂剂原子掺杂硅层的方法通常包括使掺杂剂前体的蒸气与存在于硅层上的氧化物和/或氢氧化物反应性位点反应以形成掺杂剂前体的自组装单层; 用水蒸汽水解掺杂剂前体的自组装单层以在掺杂剂前体上形成侧基羟基; 用氧化物层封闭自组装单层; 以及在有效地将掺杂剂原子从掺杂剂前体扩散到硅层中的温度下退火硅层。 可以以类似的方式形成另外的单层，由此提供受控的掺杂剂前体化合物的逐层气相沉积用于硅的受控掺杂。

    GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES
    9.
    发明申请
    GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES 有权
    具有自对准栅的石墨晶体管

    公开(公告)号：US20130299782A1

    公开(公告)日：2013-11-14

    申请号：US13492097

    申请日：2012-06-08

    申请人： ALI AFZALI-ARDAKANI ,  PHAEDON AVOURIS ,  DAMON B. FARMER ,  YU-MING LIN ,  YU ZHU

    发明人： ALI AFZALI-ARDAKANI ,  PHAEDON AVOURIS ,  DAMON B. FARMER ,  YU-MING LIN ,  YU ZHU

    IPC分类号： H01L29/772 ,  B82Y99/00

    CPC分类号： H01L29/1606 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/7781 ,  Y10S977/734

    摘要： Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.

    摘要翻译： 公开了石墨烯晶体管器件及其制造方法。 一种这样的石墨烯晶体管器件包括源电极和漏电极以及包括设置在源极和漏极之间的电介质侧壁间隔物的栅极结构。 该器件还包括与源极和漏极电极中的至少一个相邻的石墨烯层，其中源/漏电极和石墨烯层之间的界面在整个界面处保持一致的电导率。