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103 条记录 (耗时 0.021 秒)

    Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit
    1.
    发明授权
    Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
    在集成电路上选择PMOS晶体管的碳氮掺杂

    公开(公告)号：US08659112B2

    公开(公告)日：2014-02-25

    申请号：US12967109

    申请日：2010-12-14

    申请人： Mahalingam Nandakumar ,  Amitabh Jain

    发明人： Mahalingam Nandakumar ,  Amitabh Jain

    IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

    摘要翻译： 形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。 与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。 包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。 源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。 在源极和漏极之间进行源极/漏极退火。

    Method and system for improved nickel silicide
    3.
    发明授权
    Method and system for improved nickel silicide 有权
    改善硅化镍的方法和系统

    公开(公告)号：US08372750B2

    公开(公告)日：2013-02-12

    申请号：US12890100

    申请日：2010-09-24

    申请人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

    发明人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

    摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

    摘要翻译： 根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和 漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域 每个源极和漏极区域通过加热衬底。

    Antimony ion implantation for semiconductor components
    4.
    发明授权
    Antimony ion implantation for semiconductor components 有权
    半导体元件的锑离子注入

    公开(公告)号：US07795122B2

    公开(公告)日：2010-09-14

    申请号：US11725927

    申请日：2007-03-20

    申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank S. Ekbote

    发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank S. Ekbote

    IPC分类号： H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

    摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

    摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

    Activation of CMOS source/drain extensions by ultra-high temperature anneals
    5.
    发明授权
    Activation of CMOS source/drain extensions by ultra-high temperature anneals 有权
    通过超高温退火激活CMOS源极/漏极延伸

    公开(公告)号：US07615458B2

    公开(公告)日：2009-11-10

    申请号：US11764980

    申请日：2007-06-19

    申请人： Amitabh Jain ,  Manoj Mehrotra

    发明人： Amitabh Jain ,  Manoj Mehrotra

    IPC分类号： H01L21/331

    CPC分类号： H01L21/2652 ,  H01L21/2255 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/6659

    摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

    摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成栅电极。 将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。 衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

    Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region
    7.
    发明申请
    Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region 有权
    使用激光退火制造的半导体器件将应力引入通道区域

    公开(公告)号：US20090065880A1

    公开(公告)日：2009-03-12

    申请号：US11853328

    申请日：2007-09-11

    申请人： Amitabh Jain ,  Manoj Mehrotra

    发明人： Amitabh Jain ,  Manoj Mehrotra

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

    摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

    摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。

    Source/drain extension implant process for use with short time anneals
    8.
    发明授权
    Source/drain extension implant process for use with short time anneals 有权
    源/漏扩展植入过程用于短时间退火

    公开(公告)号：US07297605B2

    公开(公告)日：2007-11-20

    申请号：US10842308

    申请日：2004-05-10

    申请人： Amitabh Jain ,  Gordon Pollack

    发明人： Amitabh Jain ,  Gordon Pollack

    IPC分类号： H01L21/336 ,  H01L21/425

    CPC分类号： H01L21/26586 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

    摘要翻译： 本发明在一个实施例中提供一种用于制造金属氧化物半导体（MOS）器件（100）的工艺。 该方法包括在衬底（105）上形成栅极（120）并在衬底（105）中形成源极/漏极延伸部分（160）。 形成源极/漏极延伸部分（160）包括异常倾斜的掺杂剂注入（135）和掺杂剂注入（145）。 异常倾斜的掺杂剂注入（135）使用大于约零度的第一加速能量和倾斜角。 掺杂剂注入（145）使用高于第一加速能量的第二加速能量。 该工艺还包括执行衬底（105）的超高温退火，其中源极/漏极延伸部（160）的部分（170）在栅极（120）下方。

    Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
    10.
    发明申请
    Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor 有权
    具有位于由源/漏区产生的边界内的位错环的半导体器件及其制造方法

    公开(公告)号：US20060163651A1

    公开(公告)日：2006-07-27

    申请号：US11042415

    申请日：2005-01-25

    申请人： Antonio Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

    发明人： Antonio Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

    IPC分类号： H01L29/06

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823814 ,  H01L21/823871

    摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

    摘要翻译： 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其它步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。