公开(公告)号：US20110185332A1

公开(公告)日：2011-07-28

申请号：US12695494

申请日：2010-01-28

申请人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

发明人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

摘要翻译： 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

公开(公告)号：US07533357B2

公开(公告)日：2009-05-12

申请号：US11421863

申请日：2006-06-02

申请人： Kurt A. Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

发明人： Kurt A. Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

摘要翻译： 在初始布局规划设计阶段期间估计IC所需的分解的方法通过获得IC的配电网络中的多个节点的电压变化波形开始。 接下来，该方法计算每个电压变化波形的最小值，并选择低于最小阈值的电压变化波形。 此后，对低于最小阈值的电压变化波形执行FDA，以创建一组频率值。 这涉及对每个电压变化波形执行FFT以获得频域数据，其中导致多个节点中的电压下降的频率被滤波。 该方法然后对频域数据进行排序，其中基于振幅值，总功率，频率分量和/或虚部的振幅来顺序地布置频域数据。

公开(公告)号：US20070283299A1

公开(公告)日：2007-12-06

申请号：US11421863

申请日：2006-06-02

申请人： Kurt A Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

发明人： Kurt A Carlsen ,  Amol A. Joshi ,  Faraydon Pakbaz ,  Sanjay Upreti

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

摘要翻译： 在初始布局规划设计阶段期间估计IC所需的分解的方法通过获得IC的配电网络中的多个节点的电压变化波形开始。 接下来，该方法计算每个电压变化波形的最小值，并选择低于最小阈值的电压变化波形。 此后，对低于最小阈值的电压变化波形执行FDA，以创建一组频率值。 这涉及对每个电压变化波形执行FFT以获得频域数据，其中导致多个节点中的电压下降的频率被滤波。 该方法然后对频域数据进行排序，其中基于振幅值，总功率，频率分量和/或虚部的振幅来顺序地布置频域数据。

公开(公告)号：US20130085726A1

公开(公告)日：2013-04-04

申请号：US13251517

申请日：2011-10-03

申请人： Peter A. Habitz ,  Amol A. Joshi

发明人： Peter A. Habitz ,  Amol A. Joshi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.

摘要翻译： 方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。 方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

公开(公告)号：US08855993B2

公开(公告)日：2014-10-07

申请号：US13251517

申请日：2011-10-03

申请人： Peter A. Habitz ,  Amol A. Joshi

发明人： Peter A. Habitz ,  Amol A. Joshi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.

摘要翻译： 方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。 方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

公开(公告)号：US20130226536A1

公开(公告)日：2013-08-29

申请号：US13406897

申请日：2012-02-28

申请人： Peter A. Habitz ,  Amol A. Joshi ,  Amith Singhee ,  James E. Sundquist ,  Wangyang Zhang

发明人： Peter A. Habitz ,  Amol A. Joshi ,  Amith Singhee ,  James E. Sundquist ,  Wangyang Zhang

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036 ,  G06F17/50 ,  G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

摘要翻译： 公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的数量和类型设备。 该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。 可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。 积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。

公开(公告)号：US08656325B2

公开(公告)日：2014-02-18

申请号：US13348850

申请日：2012-01-12

申请人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

发明人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/76 ,  G06F2217/78

摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。

公开(公告)号：US08230382B2

公开(公告)日：2012-07-24

申请号：US12695494

申请日：2010-01-28

申请人： Robert J. Gauthier, Jr. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

发明人： Robert J. Gauthier, Jr. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

摘要翻译： 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

公开(公告)号：US09323875B2

公开(公告)日：2016-04-26

申请号：US13406897

申请日：2012-02-28

申请人： Peter A. Habitz ,  Amol A. Joshi ,  Amith Singhee ,  James E. Sundquist ,  Wangyang Zhang

发明人： Peter A. Habitz ,  Amol A. Joshi ,  Amith Singhee ,  James E. Sundquist ,  Wangyang Zhang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/50 ,  G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

摘要翻译： 公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的设备的数量和类型。 该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。 可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。 积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。

公开(公告)号：US20130185684A1

公开(公告)日：2013-07-18

申请号：US13348850

申请日：2012-01-12

申请人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

发明人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/76 ,  G06F2217/78

摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。