公开(公告)号：US20080062735A1

公开(公告)日：2008-03-13

申请号：US10925863

申请日：2004-08-24

申请人： Andre DeHon

发明人： Andre DeHon

IPC分类号： G11C5/06

CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/77 ,  G11C2213/81 ,  H01L23/522 ,  H01L29/0665 ,  H01L29/0673 ,  H01L2924/0002 ,  Y10S438/962 ,  Y10S977/762 ,  Y10S977/764 ,  Y10S977/767 ,  Y10S977/943 ,  H01L2924/00

摘要： Methods for obtaining codes to be implemented in coding nanoscale wires are disclosed. The methods disclosed teach how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further teach how to generate different code permutations through random misalignment and how to promote uniform code probability selection.

摘要翻译： 公开了用于获得编码纳米尺寸线中的代码的方法。 所公开的方法教导了如何通过使用旋转组代码对减少数量的纳米级线进行编码。 该方法进一步教导了如何通过随机错位生成不同的代码排列以及如何促进均匀代码概率选择。

公开(公告)号：US20070234128A1

公开(公告)日：2007-10-04

申请号：US11655745

申请日：2007-01-19

申请人： Andre DeHon ,  Nachiket Kapre

发明人： Andre DeHon ,  Nachiket Kapre

IPC分类号： G06F11/00

CPC分类号： G06F7/49942 ,  G06F7/485 ,  G06F7/508 ,  G06F7/509

摘要： An apparatus and method that use an associative calculator for calculating a sequence of non-associative operations on a set of input data, comprising: using the associative calculator to calculate from the set of input data an evaluated value of each operation of said sequence as if the non-associative operations were associative operations; detecting if some of the evaluated values are erroneous; if there are erroneous evaluated values, correcting the erroneous evaluated values; and if there are no erroneous evaluated value, outputting as the result of the sequence of non-associative operations the evaluated value of the last operation of the sequence.

摘要翻译： 一种使用关联计算器来计算一组输入数据的非关联操作序列的装置和方法，包括：使用所述关联计算器从所述输入数据集合中计算所述序列的每个操作的估计值，如同 非关联操作是关联操作; 检测某些评估值是否错误; 如果存在错误的评估值，则校正错误的评估值; 并且如果没有错误的评估值，则作为非关联操作序列的结果输出序列的最后操作的评估值。

公开(公告)号：US6052773A

公开(公告)日：2000-04-18

申请号：US471836

申请日：1995-06-06

申请人： Andre DeHon ,  Michael Bolotski ,  Thomas F. Knight, Jr.

发明人： Andre DeHon ,  Michael Bolotski ,  Thomas F. Knight, Jr.

IPC分类号： G06F15/78 ,  G06F15/00

CPC分类号： G06F9/30181 ,  G06F15/7867 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3897

摘要： A single chip microprocessor or memory device has reprogrammable characteristics according to the invention. In the case of the microprocessor, a fixed processing cell is provided as is common to perform logic calculations. A portion of the chip silicon real-estate, however, is dedicated a programmable gate array. This feature enables application-specific configurations to allow adaptation to the particular time-changing demands of the microprocessor and provide the functionality required to best serve those demands. This yields application acceleration and in system-specific functions. In other cases the configurable logic acts as network interface, which allows the same basic processor design to function in any environment to which the interface can adapt.The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units. These features lessen the impact of the data bottle-neck associated with bus communications, since the processing capability is moved to the memory in the form programmable logic, which can be configured to the needs of the specific application. The inherently large on-chip bandwidth can then be utilized to increase the speed at which bulk data is processed.

摘要翻译： 单芯片微处理器或存储器件具有根据本发明的可编程特性。 在微处理器的情况下，提供固定的处理单元，以便执行逻辑计算。 然而，芯片硅的部分区域专用于可编程门阵列。 此功能使特定应用的配置能够适应微处理器的特定时变需求，并提供最佳服务于这些需求所需的功能。 这产生了应用程序加速和系统特定的功能。 在其他情况下，可配置逻辑充当网络接口，这允许相同的基本处理器设计在接口可以适应的任何环境中起作用。 本发明还涉及具有多个存储体和与存储体相关联的可配置逻辑单元的存储器件。 提供互连以实现可配置逻辑单元之间的通信。 这些功能可以减轻与总线通信相关的数据瓶颈的影响，因为处理能力可以以可编程逻辑的形式移动到存储器，可以根据具体应用的需要进行配置。 然后可以利用固有的大的片上带宽来提高处理批量数据的速度。

公开(公告)号：US5956518A

公开(公告)日：1999-09-21

申请号：US632371

申请日：1996-04-11

申请人： Andre DeHon ,  Ethan Mirsky ,  Thomas F. Knight, Jr.

发明人： Andre DeHon ,  Ethan Mirsky ,  Thomas F. Knight, Jr.

IPC分类号： G06F15/80

CPC分类号： G06F15/8023

摘要： A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

公开(公告)号：US08552621B2

公开(公告)日：2013-10-08

申请号：US12955285

申请日：2010-11-29

申请人： Gianluca Piazza ,  Nipun Sinha ,  Timothy S. Jones ,  Zhijun Guo ,  Graham E. Wabiszewski ,  Robert Carpick ,  Andre Dehon

发明人： Gianluca Piazza ,  Nipun Sinha ,  Timothy S. Jones ,  Zhijun Guo ,  Graham E. Wabiszewski ,  Robert Carpick ,  Andre Dehon

IPC分类号： H01L41/09 ,  H01H57/00

CPC分类号： H01L41/094 ,  H01H57/00 ,  H01H2057/006

摘要： Systems and methods for operating piezoelectric switches are disclosed. A piezoelectric switching system includes a first actuator, a second actuator, and a bias voltage source. The first actuator has a first body electrode, a first gate electrode, and a first contact region. The second actuator has a second body electrode, a second gate electrode, and a second contact region. The first and second contact regions are separated by a gap. The bias voltage source applies a bias voltage to the body electrodes. The bias voltage is lower in magnitude than an actuation voltage for the switch. The gate electrodes receive a switching voltage. The switching voltage causes at least one of the first and second actuators to bend, thereby closing the gap such that the second contact region electrically contacts the first contact region. The difference between the switching voltage and the bias voltage exceeds the actuation voltage of the switch.

摘要翻译： 公开了用于操作压电开关的系统和方法。 压电开关系统包括第一致动器，第二致动器和偏置电压源。 第一致动器具有第一主体电极，第一栅极电极和第一接触区域。 第二致动器具有第二主体电极，第二栅电极和第二接触区域。 第一和第二接触区域间隔开。 偏置电压源向体电极施加偏置电压。 偏置电压的幅度要小于开关的启动电压。 栅电极接收开关电压。 开关电压导致第一和第二致动器中的至少一个弯曲，从而闭合间隙，使得第二接触区域电接触第一接触区域。 开关电压和偏置电压之间的差异超过开关的致动电压。

公开(公告)号：US20120061648A1

公开(公告)日：2012-03-15

申请号：US13301235

申请日：2011-11-21

申请人： Andre DEHON ,  Charles M. Lieber ,  John E. Savage ,  Eric Rachlin

发明人： Andre DEHON ,  Charles M. Lieber ,  John E. Savage ,  Eric Rachlin

IPC分类号： H01L27/08 ,  H01L21/77

CPC分类号： H01L29/0669 ,  B82Y10/00 ,  H01L27/10 ,  H01L27/28 ,  H01L29/0673 ,  H01L51/10

摘要： Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.

摘要翻译： 公开了一种构建包括多个纳米线（NW）的装置的方法，每个纳米线具有芯部和至少一个壳体。 该方法包括提供多个径向编码的NW，其中每个壳包含多个不同的壳材料之一; 并且通过选择性地去除或不去除要电耦合到多个介质（MW）中的各个的区域的区域内的壳体材料来区分NW中的各个。 还公开了包含径向编码的NW的纳米线阵列和用于形成纳米线阵列的计算机程序产品。

公开(公告)号：US08072005B2

公开(公告)日：2011-12-06

申请号：US11883679

申请日：2006-02-02

申请人： Andre Dehon ,  Charles M. Lieber ,  John E. Savage ,  Eric Rachlin

发明人： Andre Dehon ,  Charles M. Lieber ,  John E. Savage ,  Eric Rachlin

IPC分类号： H01L27/10

CPC分类号： H01L27/10 ,  B82Y10/00 ,  G11C2213/18 ,  G11C2213/81 ,  H03K19/177 ,  H03K19/1778 ,  Y10T428/2958

摘要： Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.

摘要翻译： 公开了一种构建包括多个纳米线（NW）的装置的方法，每个纳米线具有芯部和至少一个壳体。 该方法包括提供多个径向编码的NW，其中每个壳包含多个不同的壳材料之一; 并且通过选择性地去除或不去除要电耦合到多个介质（MW）中的各个的区域的区域内的壳体材料来区分NW中的各个。 还公开了包含径向编码的NW的纳米线阵列和用于形成纳米线阵列的计算机程序产品。

公开(公告)号：US20070214445A1

公开(公告)日：2007-09-13

申请号：US11606811

申请日：2006-11-29

申请人： Andre DeHon ,  Michael Wrighton

发明人： Andre DeHon ,  Michael Wrighton

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method and a device for performing placement of a plurality of elements for circuit design. A potential location is assigned to each element and a placement engine is assigned to each potential location. Pairing operations are performed, in parallel, between placement engines to determine whether to perform exchange of the elements associated with the engines. Exchange determination is based both on a cost function and on randomness considerations. Also self-placement is allowed, where the placement engines are implemented on the same hardware system on which the elements are to be placed.

公开(公告)号：US08883568B2

公开(公告)日：2014-11-11

申请号：US13301235

申请日：2011-11-21

申请人： Andre Dehon ,  Charles M. Lieber ,  John E. Savage ,  Eric Rachlin

发明人： Andre Dehon ,  Charles M. Lieber ,  John E. Savage ,  Eric Rachlin

IPC分类号： H01L27/10 ,  H01L29/06 ,  B82Y10/00

CPC分类号： H01L29/0669 ,  B82Y10/00 ,  H01L27/10 ,  H01L27/28 ,  H01L29/0673 ,  H01L51/10

摘要： Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.

摘要翻译： 公开了一种构建包括多个纳米线（NW）的装置的方法，每个纳米线具有芯部和至少一个壳体。 该方法包括提供多个径向编码的NW，其中每个壳包含多个不同的壳材料之一; 并且通过选择性地去除或不去除要电耦合到多个介质（MW）中的各个的区域的区域内的壳体材料来区分NW中的各个。 还公开了包含径向编码的NW的纳米线阵列和用于形成纳米线阵列的计算机程序产品。

公开(公告)号：US20070127280A1

公开(公告)日：2007-06-07

申请号：US10853907

申请日：2004-05-25

申请人： Andre DeHon ,  Helia Naeimi

发明人： Andre DeHon ,  Helia Naeimi

IPC分类号： G11C5/06

CPC分类号： H03K19/1776 ,  B82Y10/00 ,  G11C5/063 ,  G11C8/10 ,  G11C11/34 ,  G11C11/54 ,  G11C29/025 ,  G11C29/08 ,  G11C29/76 ,  G11C29/816 ,  G11C29/832 ,  G11C2213/81 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/1778 ,  Y10S977/963

摘要： A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.

摘要翻译： 一种用于构建和寻址具有已知地址的纳米尺度存储器并且用于容忍在制造或器件操作寿命期间可能出现的缺陷的方法。 在施工期间，地址的纳米级电线随机组装。 在编程阶段期间，使用其随机地址通过微量输入随机选择纳米线，并且所需的地址码与所选择的纳米尺度线相关联。 存储器地址与代码相关联，然后在从/到存储器的读/写操作期间使用已知代码进行选择。