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    Wear leveling of solid state disks distributed in a plurality of redundant array of independent disk ranks
    1.
    发明授权
    Wear leveling of solid state disks distributed in a plurality of redundant array of independent disk ranks 有权
    分散在独立磁盘排列的多个冗余阵列中的固态磁盘的磨损均衡

    公开(公告)号：US08639877B2

    公开(公告)日：2014-01-28

    申请号：US12495244

    申请日：2009-06-30

    申请人： Michael Thomas Benhase ,  Andrew Dale Walls

    发明人： Michael Thomas Benhase ,  Andrew Dale Walls

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/0246 ,  G06F11/108 ,  G06F11/1096 ,  G06F2212/7208 ,  G06F2212/7211

    摘要： A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present.

    摘要翻译： 计算设备将多个固态磁盘分配给独立磁盘（RAID）等级的多个冗余阵列，其中在多个RAID等级的每个RAID等级中不存在不同的固态磁盘。 计算装置从多个固态盘确定至少一个所选择的固态盘，其中与多个固体中的其他固态盘相比，所述至少一个所选择的固态盘被估计已经经历了更大量的磨损 状态磁盘。 与存在至少一个所选固态盘的那些RAID等级相比，将相对更多的数据和奇偶校验信息写入到其中不存在至少一个所选固态盘的那些RAID等级。

    REDUNDANT SOLID STATE DISK SYSTEM VIA INTERCONNECT CARDS
    2.
    发明申请
    REDUNDANT SOLID STATE DISK SYSTEM VIA INTERCONNECT CARDS 失效
    冗余固态盘系统通过互连卡

    公开(公告)号：US20120159004A1

    公开(公告)日：2012-06-21

    申请号：US13405056

    申请日：2012-02-24

    申请人： Lee Dale Cleveland ,  Seth David Lewis ,  Christopher William Mann ,  Andrew Dale Walls

    发明人： Lee Dale Cleveland ,  Seth David Lewis ,  Christopher William Mann ,  Andrew Dale Walls

    IPC分类号： G06F3/00

    CPC分类号： G06F11/2089 ,  G06F11/1441 ,  G06F11/2056

    摘要： A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.

    摘要翻译： 配置第一互连卡，其中第一控制器包括在第一互连卡中。 配置了耦合到第一互连卡的第二互连卡，其中第二控制器被包括在第二互连卡中。 响应于包括在第一互连卡中的第一控制器的故障，通过包括在第二互连卡中的第二控制器来控制第一互连卡。 响应于包括在第二互连卡中的第二控制器的故障，通过包括在第一互连卡中的第一控制器来控制第二互连卡。

    Multi-node configuration of processor cards connected via processor fabrics
    3.
    发明授权
    Multi-node configuration of processor cards connected via processor fabrics 有权
    通过处理器接口连接的处理器卡的多节点配置

    公开(公告)号：US08095691B2

    公开(公告)日：2012-01-10

    申请号：US12830275

    申请日：2010-07-02

    申请人： William Garrett Verdoorn, Jr. ,  Andrew Dale Walls

    发明人： William Garrett Verdoorn, Jr. ,  Andrew Dale Walls

    IPC分类号： G06F11/07

    CPC分类号： G06F15/16

    摘要： Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

    摘要翻译： 提供了一种系统，其包括第一节点，其包括多个处理器卡，每个处理器卡均包括处理器结构，其中第一节点中的处理器卡经由其处理器结构连接; 第二节点包括多个处理器卡，每个处理器卡包括处理器结构，其中第二节点中的处理器卡经由其处理器结构连接; 以及多个通信接口，其中每个接口将第二节点中的一个处理器卡连接到第一节点中的一个处理器卡，以实现连接的处理器卡之间的通信，以协调第一和第二节点之间连接的处理器卡之间的处理器操作。

    MULTI-CHARACTER ADAPTER CARD
    5.
    发明申请
    MULTI-CHARACTER ADAPTER CARD 失效
    多字符适配卡

    公开(公告)号：US20080301345A1

    公开(公告)日：2008-12-04

    申请号：US11754821

    申请日：2007-05-29

    申请人： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

    发明人： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

    IPC分类号： G06F13/00

    CPC分类号： G06F13/385

    摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

    摘要翻译： 根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。 逻辑芯片连接到电路板以向适配器卡提供功能。 一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。 该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。 提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

    Method and apparatus for multiplexing multiple protocol handlers on a shared memory bus
    6.
    发明申请
    Method and apparatus for multiplexing multiple protocol handlers on a shared memory bus 失效
    用于在共享存储器总线上复用多个协议处理程序的方法和装置

    公开(公告)号：US20080109577A1

    公开(公告)日：2008-05-08

    申请号：US11532936

    申请日：2006-09-19

    申请人： Michael Joseph Azevedo ,  Andrew Dale Walls

    发明人： Michael Joseph Azevedo ,  Andrew Dale Walls

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4243 ,  H04L47/50 ,  H04L69/18

    摘要： Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

    摘要翻译： 协议多路复用器被配置为接收多个通信链路，每个链路以多个通信协议之一操作。 协议处理器根据用于特定通信链路的通信协议转换接收的数据并对数据进行帧化。 端口复用器将接收到的帧分为数据帧和控制帧。 数据帧被复用到单个数据总线上，并且控制帧被复用到单个控制总线上以增加协议多路复用器的性能。

    ASSISTED TRACE FACILITY TO IMPROVE CPU CACHE PERFORMANCE
    7.
    发明申请
    ASSISTED TRACE FACILITY TO IMPROVE CPU CACHE PERFORMANCE 失效
    辅助跟踪功能来提高CPU高速缓存的性能

    公开(公告)号：US20080065810A1

    公开(公告)日：2008-03-13

    申请号：US11530393

    申请日：2006-09-08

    申请人： Carol Spanel ,  Andrew Dale Walls

    发明人： Carol Spanel ,  Andrew Dale Walls

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F11/348 ,  G06F11/3471

    摘要： A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

    摘要翻译： 用于在保存缓存资源的同时记录跟踪数据的系统和方法包括生成跟踪数据并创建包含跟踪数据的高速缓存行。 为缓存线分配一个标签，该标签对应于指定用于处理跟踪数据的中间地址。 高速缓存线还包括在其中嵌入存储跟踪数据的存储器中的实际地址，其可以包括实际地址或虚拟地址。 高速缓存行可以在中间地址处被接收并被解析以读取实际地址。 然后可以将跟踪数据写入与实际地址相对应的存储器中的位置。 通过路由跟踪数据通过指定的中间地址，CPU缓存可以保存为其他更重要或更频繁访问的数据。

    Apparatus, system, and method for adapter card failover
    10.
    发明授权
    Apparatus, system, and method for adapter card failover 有权
    适配卡故障切换的装置，系统和方法

    公开(公告)号：US07870417B2

    公开(公告)日：2011-01-11

    申请号：US11738142

    申请日：2007-04-20

    申请人： Stephen L. Blinick ,  Cheng-Chung Song ,  Carol Spanel ,  Andrew Dale Walls

    发明人： Stephen L. Blinick ,  Cheng-Chung Song ,  Carol Spanel ,  Andrew Dale Walls

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2038 ,  G06F11/2033 ,  G06F11/2046

    摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

    摘要翻译： 公开了用于适配器卡故障切换的装置，系统和方法。 开关模块通过作为所有者处理器的第一端口将第一处理器复合体连接到适配器卡。 所有者处理器复合体管理适配器卡，但第二个端口除外，并从适配器卡接收错误消息。 交换机模块通过第二端口进一步将第二处理器复合体连接到适配器卡，作为非所有者处理器复合体。 非所有者处理器复合体管理第二个端口。 检测模块检测第一处理器复杂的故障。 设置模块修改交换机模块以将所有者处理器复杂化，将第二处理器复合体逻辑连接到适配器卡，并根据检测到故障从逻辑上断开第一个处理器复合体与适配器卡的连接。