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    Gate trim process using either wet etch or dry etch approach to target CD for selected transistors
    3.
    发明授权
    Gate trim process using either wet etch or dry etch approach to target CD for selected transistors 有权
    使用湿蚀刻或干法蚀刻方法对所选晶体管靶CD进行栅极修整处理

    公开(公告)号：US08067314B2

    公开(公告)日：2011-11-29

    申请号：US12424023

    申请日：2009-04-15

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L21/76

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    Memory device etch methods
    4.
    发明授权
    Memory device etch methods 有权
    存储器件蚀刻方法

    公开(公告)号：US07972951B2

    公开(公告)日：2011-07-05

    申请号：US12688477

    申请日：2010-01-15

    申请人： Angela T. Hui ,  Jihwan Choi

    发明人： Angela T. Hui ,  Jihwan Choi

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

    摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF4）和三氟甲烷（CHF 3）在内的蚀刻化学品，以蚀刻 至少控制门层。

    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS
    5.
    发明申请
    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS 有权
    使用蚀刻蚀刻或干蚀刻蚀刻技术的GATE TRIM工艺可用于所选晶体管的目标光盘

    公开(公告)号：US20100264519A1

    公开(公告)日：2010-10-21

    申请号：US12424023

    申请日：2009-04-15

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L29/423 ,  H01L21/306

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    Memory device etch methods
    6.
    发明授权
    Memory device etch methods 有权
    存储器件蚀刻方法

    公开(公告)号：US07670959B2

    公开(公告)日：2010-03-02

    申请号：US11616085

    申请日：2006-12-26

    申请人： Angela T. Hui ,  Jihwan Choi

    发明人： Angela T. Hui ,  Jihwan Choi

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

    摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF4）和三氟甲烷（CHF 3）在内的蚀刻化学品，以蚀刻 至少控制门层。

    SEMICONDUCTOR CONTACT FORMATION SYSTEM AND METHOD
    7.
    发明申请
    SEMICONDUCTOR CONTACT FORMATION SYSTEM AND METHOD 有权
    半导体接触形成系统和方法

    公开(公告)号：US20090294969A1

    公开(公告)日：2009-12-03

    申请号：US12539480

    申请日：2009-08-11

    申请人： Wenmei LI ,  Angela T. HUI ,  Dawn HOPPER ,  Kouros GHANDEHARI

    发明人： Wenmei LI ,  Angela T. HUI ,  Dawn HOPPER ,  Kouros GHANDEHARI

    IPC分类号： H01L23/522

    CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

    摘要翻译： 本发明是一种半导体接触形成系统和方法。 接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。 该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。 通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。 导电材料（例如，钨）沉积在接触区域中。

    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices
    9.
    发明授权
    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices 有权
    单独使用BPTEOS ILD或BPTEOS ILD的薄的未掺杂TEOS来改善多位存储器件中的电荷损耗和接触电阻

    公开(公告)号：US07157335B1

    公开(公告)日：2007-01-02

    申请号：US10917562

    申请日：2004-08-13

    申请人： Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela T. Hui ,  Yi He ,  Brian Mooney ,  Jean Yei-Mei Yang ,  Mark T. Ramsbey

    发明人： Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela T. Hui ,  Yi He ,  Brian Mooney ,  Jean Yei-Mei Yang ,  Mark T. Ramsbey

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

    摘要翻译： 本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。 使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。 本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。 相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。 此外，本发明包括前述的未掺杂的TEOS衬垫。