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441 条记录 (耗时 0.06 秒)

    Test structure and calibration method
    4.
    发明授权
    Test structure and calibration method 有权
    测试结构和校准方法

    公开(公告)号：US08829518B2

    公开(公告)日：2014-09-09

    申请号：US13231516

    申请日：2011-09-13

    申请人： Jeffrey C. Maling ,  Anthony K. Stamper ,  Eric J. White

    发明人： Jeffrey C. Maling ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/10

    CPC分类号： B81C99/004

    摘要： A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.

    摘要翻译： 用于测量微机电系统（MEMS）腔体高度结构和校准方法的测试结构。 该方法包括在多个电极上形成牺牲腔材料并在牺牲腔材料中形成开口。 该方法还包括在开口中形成透明或基本上透明的材料以形成透明或基本上透明的窗口。 该方法还包括基于通过透明或基本上透明的窗口获得的测量值调整牺牲腔材料的厚度。

    Interconnect structures and design structures for a radiofrequency integrated circuit
    5.
    发明授权
    Interconnect structures and design structures for a radiofrequency integrated circuit 有权
    射频集成电路的互连结构和设计结构

    公开(公告)号：US08791545B2

    公开(公告)日：2014-07-29

    申请号：US13560446

    申请日：2012-07-27

    申请人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/016 ,  H01L28/20 ,  H01L28/40

    摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

    摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

    Wiring structure and method of forming the structure
    6.
    发明授权
    Wiring structure and method of forming the structure 有权
    布线结构及形成方法

    公开(公告)号：US08569888B2

    公开(公告)日：2013-10-29

    申请号：US13114079

    申请日：2011-05-24

    申请人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    发明人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

    摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

    INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
    9.
    发明申请
    INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE 有权
    具有非晶硅光束的集成半导体器件，制造方法和设计结构

    公开(公告)号：US20130119491A1

    公开(公告)日：2013-05-16

    申请号：US13294615

    申请日：2011-11-11

    申请人： Stephen E. LUCE ,  Anthony K. Stamper

    发明人： Stephen E. LUCE ,  Anthony K. Stamper

    IPC分类号： H01L29/84 ,  G06F9/45 ,  H01L21/02

    CPC分类号： H03H9/02007 ,  G06F17/5072 ,  H01L21/84 ,  H01L27/1203 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155

    摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively.

    摘要翻译： 公开了与CMOS工艺，制造方法和设计结构集成的体声波滤波器和/或体声波谐振器。 该方法包括形成至少一个包含非晶硅材料的光束并在非晶硅光束上并邻近其提供绝缘体材料。 该方法还包括通过绝缘体材料形成通孔并暴露非晶硅束下面的材料。 该方法还包括在通孔和非晶硅光束上提供牺牲材料。 该方法还包括在牺牲材料上并在绝缘体材料之上提供盖子。 该方法还包括通过盖子排出牺牲材料和下面的材料，以分别在非晶硅束的上方形成上腔，并在非晶硅束的下方形成下腔。

    Increasing an electrical resistance of a resistor by oxidation
    10.
    发明授权
    Increasing an electrical resistance of a resistor by oxidation 有权
    通过氧化增加电阻的电阻

    公开(公告)号：US08440522B2

    公开(公告)日：2013-05-14

    申请号：US11968686

    申请日：2008-01-03

    申请人： Arne W. Ballantine ,  Daniel C. Edelstein ,  Anthony K. Stamper

    发明人： Arne W. Ballantine ,  Daniel C. Edelstein ,  Anthony K. Stamper

    IPC分类号： H01L21/8234 ,  H01L21/20

    CPC分类号： C23C8/02 ,  C23C8/04 ,  C23C8/10 ,  C23C8/24 ,  C25D11/00 ,  C25D11/02 ,  C25D11/026 ,  H01C7/006 ,  H01C17/26 ,  H01L21/263 ,  H01L27/0802 ,  H01L29/8605 ,  Y10S257/904 ,  Y10S257/914

    摘要： A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

    摘要翻译： 一种用于增加在半导体结构内的电阻器的电阻的方法。 电阻的表面层的一部分被氧颗粒氧化。 在一个实施方案中，表面层的分数由颗粒束加热，使得半导体结构在包含作为气态含氧分子的氧颗粒的室内。 在一个实施方案中，将半导体结构浸入包括氧颗粒的化学溶液中，其中氧颗粒包括在加压下溶解在化学溶液中的含氧液体分子，氧离子或含氧气体。 在一个实施例中，测试电阻器以确定在用氧颗粒氧化后电阻器的电阻是否在预定目标电阻的容限内。