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公开(公告)号：US08850091B1
公开(公告)日：2014-09-30
申请号：US13745804
申请日：2013-01-20
申请人： Vijay Karamcheti , Ashwin Narasimha
发明人： Vijay Karamcheti , Ashwin Narasimha
CPC分类号： G06F1/30 , G06F1/266 , G06F3/061 , G06F3/0659 , G06F3/0685 , G06F11/3058 , G06F12/0246 , G06F2212/7208
摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。
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2.发明授权Methods for early write termination and power failure with non-volatile memory 有权使用非易失性存储器的早期写入终止和电源故障的方法公开(公告)号：US08516172B1
公开(公告)日：2013-08-20
申请号：US13163481
申请日：2011-06-17
申请人： Vijay Karamcheti , Ashwin Narasimha
发明人： Vijay Karamcheti , Ashwin Narasimha
IPC分类号： G06F13/12
CPC分类号： G06F1/30 , G06F1/266 , G06F3/061 , G06F3/0659 , G06F3/0685 , G06F11/3058 , G06F12/0246 , G06F2212/7208
摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。
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3.发明授权Multiple-port memory device comprising single-port memory device with supporting control circuitry 有权多端口存储器件包括具有支持控制电路的单端口存储器件公开(公告)号：US08514652B2
公开(公告)日：2013-08-20
申请号：US13038662
申请日：2011-03-02
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/10 , G11C7/1075 , G11C11/418
摘要： A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device. In an illustrative embodiment, the single-port memory device operates at a clock rate that is an integer multiple of a clock rate of first and second memory drivers that supply the input signals to and receive the output signals from the respective first and second ports of the multiple-port memory device.
摘要翻译： 具有至少第一和第二端口的多端口存储器设备被配置为支持读取和写入操作。 多端口存储器件还包括耦合在第一和第二端口与单端口存储器件之间的单端口存储器件和控制电路。 控制电路被配置为将在多端口存储器件的第一和第二端口上接收的输入信号复用到单端口存储器件的单个端口的相应输入时隙中，并且解复用单端口的输出时隙 的单端口存储器件的输出信号转换成通过多端口存储器件的第一和第二端口提供的输出信号。 在说明性实施例中，单端口存储器件以时钟速率工作，时钟速率是第一和第二存储器驱动器的时钟速率的整数倍，第一和第二存储器驱动器的输入信号提供给相应的第一和第二端口 多端口存储设备。
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4.发明申请MULTIPLE-PORT MEMORY DEVICE COMPRISING SINGLE-PORT MEMORY DEVICE WITH SUPPORTING CONTROL CIRCUITRY 有权包含支持控制电路的单端口存储器件的多端口存储器件公开(公告)号：US20120224435A1
公开(公告)日：2012-09-06
申请号：US13038662
申请日：2011-03-02
CPC分类号： G11C8/16 , G11C7/10 , G11C7/1075 , G11C11/418
摘要： A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device. In an illustrative embodiment, the single-port memory device operates at a clock rate that is an integer multiple of a clock rate of first and second memory drivers that supply the input signals to and receive the output signals from the respective first and second ports of the multiple-port memory device.
摘要翻译： 具有至少第一和第二端口的多端口存储器设备被配置为支持读取和写入操作。 多端口存储器件还包括耦合在第一和第二端口与单端口存储器件之间的单端口存储器件和控制电路。 控制电路被配置为将在多端口存储器件的第一和第二端口上接收的输入信号复用到单端口存储器件的单个端口的相应输入时隙中，并且解复用单端口的输出时隙 的单端口存储器件的输出信号转换成通过多端口存储器件的第一和第二端口提供的输出信号。 在说明性实施例中，单端口存储器件以时钟速率工作，时钟速率是第一和第二存储器驱动器的时钟速率的整数倍，第一和第二存储器驱动器的输入信号提供给相应的第一和第二端口 多端口存储设备。
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5.发明授权Replaceable non-volatile memory apparatus with a plurality of pluggable electrical connectors 有权具有多个可插拔电连接器的可更换的非易失性存储装置公开(公告)号：US08706932B1
公开(公告)日：2014-04-22
申请号：US13163544
申请日：2011-06-17
IPC分类号： G06F13/12
CPC分类号： G06F13/1694 , G06F13/1657
摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。
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公开(公告)号：US08677037B1
公开(公告)日：2014-03-18
申请号：US13163461
申请日：2011-06-17
申请人： Vijay Karamcheti , Ashwin Narasimha
发明人： Vijay Karamcheti , Ashwin Narasimha
IPC分类号： G06F13/12
CPC分类号： G06F13/1642 , G06F13/1657 , G06F13/1694
摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。
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7.发明授权Methods for upgrading, diagnosing, and maintaining replaceable non-volatile memory 有权升级，诊断和维护可更换的非易失性存储器的方法公开(公告)号：US08650343B1
公开(公告)日：2014-02-11
申请号：US13163571
申请日：2011-06-17
CPC分类号： G06F13/1694 , G06F13/1657 , Y02D10/14
摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。
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8.发明授权Methods for early write termination into non-volatile memory with metadata write operations 有权使用元数据写操作将早期写入终止到非易失性存储器的方法公开(公告)号：US08429318B1
公开(公告)日：2013-04-23
申请号：US13163493
申请日：2011-06-17
申请人： Vijay Karamcheti , Ashwin Narasimha
发明人： Vijay Karamcheti , Ashwin Narasimha
IPC分类号： G06F13/12
CPC分类号： G06F13/1657
摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。
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公开(公告)号：US08639863B1
公开(公告)日：2014-01-28
申请号：US13163561
申请日：2011-06-17
IPC分类号： G06F13/12
CPC分类号： G06F13/1684 , Y02D10/14
摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。
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10.发明授权Methods for data redundancy across replaceable non-volatile memory storage devices 有权可更换非易失性存储设备的数据冗余方法公开(公告)号：US08689042B1
公开(公告)日：2014-04-01
申请号：US13163581
申请日：2011-06-17
IPC分类号： G06F11/00
CPC分类号： G06F13/1694 , G06F13/1657 , Y02D10/14
摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。
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