-
公开(公告)号：US5389567A
公开(公告)日：1995-02-14
申请号：US241136
申请日：1994-05-10
IPC分类号： H01L27/105 , G11B17/028 , G11C14/00 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/70
摘要： The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.
摘要翻译： 本发明涉及一种具有双层浮置栅极的单晶体管非易失性DRAM单元，以在电源中断期间允许存储电容器的内容被传送到浮动栅极。 浮动栅极的第一层通过隧道氧化物与存储电容器的存储节点分离，以允许浮置栅极和存储电容器之间的电子隧穿。 在本发明的另一个实施例中，双电子注入器结构设置在单层浮动和存储节点之间，以允许电子注入浮动栅极和存储节点之间。 在本发明的另一个实施例中，实现擦除栅极以去除浮动栅极上的电荷。 擦除栅极可以通过隧道氧化物或单个电子注入器结构与浮动栅极分离，以允许电子从浮动栅极行进到擦除栅极。
-
公开(公告)号：US5315142A
公开(公告)日：1994-05-24
申请号：US855956
申请日：1992-03-23
申请人： Alexandre Acovic , Ching-Hsiang Hsu , Being S. Wu
发明人： Alexandre Acovic , Ching-Hsiang Hsu , Being S. Wu
IPC分类号： H01L21/8247 , G11C16/12 , G11C16/14 , H01L21/336 , H01L21/8242 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L27/10844 , G11C16/12 , G11C16/14 , H01L27/115 , H01L29/66825 , H01L29/7883
摘要： The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate. A control gate overlies the floating gate and the control gate is separated from the floating gate by a separate dielectric layer. The second silicon dioxide layer is relatively thin so that tunneling of electrons between the vertical sidewalls which incorporate the source and drain regions and the floating gate will occur. Tunnelling is the mechanism which charges and discharges the floating gate. The trench EEPROM memory structure of the present invention occupies a small amount of surface area while maintaining a high coupling ratio between the control gate and the floating gate. The high coupling ratio between the floating-gate and the control-gate is maintained because the floating gate is butted to isolation oxide on two sides of the trench. The trench EEPROM memory structure of the present invention also reduces program and erase time because the floating gate can be programmed or charged through either the source or drain regions in many cells at one time.
-
公开(公告)号：US5567635A
公开(公告)日：1996-10-22
申请号：US245724
申请日：1994-05-17
申请人： Alexandre Acovic , Ching-Hsiang Hsu , Being S. Wu
发明人： Alexandre Acovic , Ching-Hsiang Hsu , Being S. Wu
IPC分类号： H01L21/8247 , G11C16/12 , G11C16/14 , H01L21/336 , H01L21/8242 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10844 , G11C16/12 , G11C16/14 , H01L27/115 , H01L29/66825 , H01L29/7883
摘要： The objects of the present invention are accomplished by merging a MOS-FET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate.
摘要翻译： 本发明的目的是通过将MOS-FET器件和浮栅合并成三维沟槽结构来实现的。 沟槽器件单元具有四个垂直边和底部。 沟槽的底部形成EEPROM单元的转移FET的沟道区。 重掺杂源极和漏极区域形成在沟槽的两个垂直侧壁上并相对地面对。 重掺杂区域覆盖整个侧壁并且具有大于沟槽深度的深度，使得沟道区域由沟槽的底部限定。 沟槽的剩余的两个垂直侧壁由隔离氧化物形成。 第一二氧化硅层覆盖沟槽的底部并形成电池器件的栅极氧化物的一部分。 第二个二氧化硅层覆盖沟槽的垂直侧壁。 第二二氧化硅层相对于栅极氧化物层相对较薄。 第二二氧化硅层将源极和漏极区域与覆盖第一和第二二氧化硅层的浮置栅极分开。 浮置栅极与所有四个沟槽侧壁重叠，并且基本上增加了浮动栅极和控制栅极之间的耦合。
-
公开(公告)号：US5331188A
公开(公告)日：1994-07-19
申请号：US841343
申请日：1992-02-25
IPC分类号： H01L27/105 , G11B17/028 , G11C14/00 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/68 , G11C11/24
摘要： The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.
摘要翻译： 本发明涉及一种具有双层浮置栅极的单晶体管非易失性DRAM单元，以在电源中断期间允许存储电容器的内容被传送到浮动栅极。 浮动栅极的第一层通过隧道氧化物与存储电容器的存储节点分离，以允许浮置栅极和存储电容器之间的电子隧穿。 在本发明的另一个实施例中，双电子注入器结构设置在单层浮动和存储节点之间，以允许电子注入浮动栅极和存储节点之间。 在本发明的另一个实施例中，实现擦除栅极以去除浮动栅极上的电荷。 擦除栅极可以通过隧道氧化物或单个电子注入器结构与浮动栅极分离，以允许电子从浮动栅极行进到擦除栅极。
-
-
-
搜索结果
4 条记录 (耗时 0.012 秒)