公开(公告)号：US20120098096A1

公开(公告)日：2012-04-26

申请号：US12909632

申请日：2010-10-21

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 双极晶体管至少包括具有不同的第一和第二EB结深度的至少第一和第二连接的发射极 - 基极（EB）结，以及具有更大的第三深度的掩埋层（BL）集电极。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域覆盖第二EB结位置，从而提供其较浅的EB结深度。 BL收集器不是第一EB结的底部，并且与其横向间隔可变量以便于调节晶体管的性质。 在其他实施例中，BL收集器可以位于第二EB结的至少一部分的下面。 相反导电类型的区域过度叠加并且位于相对轻掺杂的BL集电极，从而保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

公开(公告)号：US20110147893A1

公开(公告)日：2011-06-23

申请号：US13041531

申请日：2011-03-07

申请人： Xin Lin ,  Bernhard H. Grote ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/70

CPC分类号： H01L29/7322 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272

摘要： By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required.

摘要翻译： 通过提供一种新颖的双极器件设计实现，标准CMOS工艺可以不变地用于制造有用的双极晶体管和具有可调特性的其它双极器件，通过部分阻塞用于晶体管基极的P或N阱掺杂。 这提供了具有可调底座宽度的驼峰形基部区域，从而实现例如比仅用未修改的CMOS工艺可获得的增益更高的增益。 通过进一步部分地阻挡用于形成双极晶体管的发射极的源极/漏极掺杂步骤，可以进一步改变发射极形状和有效基极宽度，以提供对双极器件性质的附加控制。 因此，这些实施例包括对被配置为获得期望的器件特性的与双极器件相关联的掩模的规定修改。 CMOS工艺步骤和流程否则不变，不需要额外的工艺步骤。

公开(公告)号：US20090315145A1

公开(公告)日：2009-12-24

申请号：US12142115

申请日：2008-06-19

申请人： Xin Lin ,  Bernhard H. Grote ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L21/331 ,  H01L29/73

CPC分类号： H01L29/7322 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272

摘要： By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or N well doping (25) used for the transistor base (581). This provides a hump-shaped base (583, 584) region with an adjustable base width (79), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (101-104) alone. By further partially blocking the source/drain doping step (107) used to form the emitter (74) of the bipolar transistor (80), the emitter shape and effective base width (79) can be further varied to provide additional control over the bipolar device (80) properties. The embodiments thus include prescribed modifications to the masks (57, 62, 72, 46) associated with the bipolar device (80) that are configured to obtain desired device properties. The CMOS process steps (105-109) and flow are otherwise unaltered and no additional process steps are required.

摘要翻译： 通过提供一种新颖的双极器件设计实现，标准CMOS工艺（105-109）可以不变地用于制造有用的双极晶体管（80）和其他具有可调整特性的双极器件，通过部分阻塞使用的P或N阱掺杂（25） 用于晶体管基极（581）。 这提供了具有可调底座宽度（79）的驼峰形基部（583,584）区域，从而实现例如比仅用未修改的CMOS工艺（101-104）可获得的增益更高的增益。 通过进一步部分地阻挡用于形成双极晶体管（80）的发射极（74）的源/漏掺杂步骤（107），可以进一步改变发射极形状和有效基极宽度（79），以提供对双极晶体管 设备（80）属性。 因此，这些实施例包括与被配置为获得期望的器件特性的与双极器件（80）相关联的掩模（57,62,72,46）的规定修改。 CMOS工艺步骤（105-109）和流程否则不变，并且不需要额外的工艺步骤。

公开(公告)号：US08922227B2

公开(公告)日：2014-12-30

申请号：US13043075

申请日：2011-03-08

申请人： Chad S. Dawson ,  Bernhard H. Grote ,  Woo Tae Park

发明人： Chad S. Dawson ,  Bernhard H. Grote ,  Woo Tae Park

IPC分类号： G01R27/08 ,  G01R29/24

CPC分类号： G01R29/24

摘要： Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output.

摘要翻译： 提供了用于检测在其上形成有感测装置的半导体衬底上的表面电荷的系统和方法。 示例性感测系统包括其上形成有感测装置的半导体衬底和耦合到感测装置的模块。 当向半导体衬底施加第一电压时，模块获得从感测装置输出的第一电压，当向半导体衬底施加第二电压时获得从感测装置输出的第二电压，并且检测表面上的电荷 基于第一电压输出和第二电压输出之间的差的半导体衬底。

公开(公告)号：US08384184B2

公开(公告)日：2013-02-26

申请号：US12882899

申请日：2010-09-15

申请人： Tahir A. Khan ,  Bernhard H. Grote ,  Vishnu K. Khemka ,  Ronghua Zhu

发明人： Tahir A. Khan ,  Bernhard H. Grote ,  Vishnu K. Khemka ,  Ronghua Zhu

IPC分类号： H01L29/78

CPC分类号： H01L29/66681 ,  H01L21/02107 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.

摘要翻译： 这里介绍一种半导体器件和相关的制造工艺。 该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。 该器件还包括第二，第三，第四和第五半导体区域。 第二半导体区域位于第一半导体区域的上方，具有第二导电型。 第三半导体区域位于第二半导体区域的上方，具有第一导电型。 第四半导体区域位于第三半导体区域的上方，具有第二导电型。 第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。

公开(公告)号：US08791546B2

公开(公告)日：2014-07-29

申请号：US12909632

申请日：2010-10-21

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L29/73 ,  H01L29/735 ,  H01L29/70

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 双极晶体管至少包括具有不同的第一和第二EB结深度的至少第一和第二连接的发射极 - 基极（EB）结，以及具有更大的第三深度的掩埋层（BL）集电极。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域覆盖第二EB结位置，从而提供其较浅的EB结深度。 BL收集器不是第一EB结的底部，并且与其横向间隔可变量以便于调节晶体管的性质。 在其他实施例中，BL收集器可以位于第二EB结的至少一部分的下面。 相反导电类型的区域过度叠加并且位于相对轻掺杂的BL集电极，从而保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

公开(公告)号：US08344481B2

公开(公告)日：2013-01-01

申请号：US13041531

申请日：2011-03-07

申请人： Xin Lin ,  Bernhard H. Grote ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66

CPC分类号： H01L29/7322 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272

摘要： By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required.

摘要翻译： 通过提供一种新颖的双极器件设计实现，标准CMOS工艺可以不变地用于制造有用的双极晶体管和具有可调特性的其它双极器件，通过部分阻塞用于晶体管基极的P或N阱掺杂。 这提供了具有可调底座宽度的驼峰形基部区域，从而实现例如比仅用未修改的CMOS工艺可获得的增益更高的增益。 通过进一步部分地阻挡用于形成双极晶体管的发射极的源极/漏极掺杂步骤，可以进一步改变发射极形状和有效基极宽度，以提供对双极器件性质的附加控制。 因此，这些实施例包括对被配置为获得期望的器件特性的与双极器件相关联的掩模的规定修改。 CMOS工艺步骤和流程否则不变，不需要额外的工艺步骤。

公开(公告)号：US07608908B1

公开(公告)日：2009-10-27

申请号：US12125613

申请日：2008-05-22

申请人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

IPC分类号： H01L29/00 ,  H01L29/167

CPC分类号： H01L21/76264

摘要： Higher voltage device isolation structures (40, 60, 70, 80, 90, 90′) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24″). One or more dielectric lined deep isolation trenches (27, 27′, 27″, 27′″) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22″) is found to occur preferentially where the buried layer (24, 24″) intersects the dielectric sidewalls (273, 274; 273′, 274′; 273″, 274″) of the trench (27, 27′, 27″, 27′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42″, 62, 72, 82) of the same conductivity type as the buried layer (24, 24″), underlying the buried layer (24, 24″) at the trench sidewalls (273, 274; 273′, 274′; 273″, 274″). The more lightly doped region's (42, 42″, 62, 72, 82) dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (24, 24″) and it extends substantially entirely beneath the buried layer (24, 24″) or to a distance (724, 824) extending about 0.5 to 2.0 micro-meters from the trench sidewall (273, 274; 273′, 274′; 273″, 274″). In a preferred embodiment, the trench (27, 27′) is split into two portions (271, 272; 271′, 272′) with the semiconductor therein (475, 675, 775, 875) ohmically coupled to the substrate (22).

摘要翻译： 为具有强掺杂掩埋层（24,24“）的半导体集成电路提供更高电压器件隔离结构（40,60,70,80,90,90'）。 一个或多个电介质衬里的深隔离沟槽（27,27'，27“，27”'）分隔相邻的器件区域（411,412; 611,612; 711,712; 811,812; 911,912）。 发现器件区域（411,412; 611,612; 711,712; 811,812; 911,912）和相对掺杂的衬底（22,22“）之间的电击穿（BVdss）优先发生在埋置 层（24,24“）与沟槽（27,27'，27”，27“'）的电介质侧壁（273,274; 273'，274'; 273”，274“）相交。 通过提供与掩埋层下面的掩埋层（24,24“）相同的导电类型的更轻掺杂区域（42,42”，62,72,82）来增加击穿电压（BVdss） （273,274; 273'，274'; 273“，”274“）上。 掺杂浓度越高的掺杂区越好，比掩埋层（24,24“）要小1〜4埃，比埋入层（24，24”）大致全部下降， 距离沟槽侧壁（273,274; 273'，274'; 273“，”274“）延伸约0.5至2.0微米的距离（724,824）。 在优选实施例中，沟槽（27,27'）被分成两部分（271,272; 271'，272'），其中半导体在其中欧姆耦合到衬底（22），其中（475,675,775,875） 。

公开(公告)号：US08511170B2

公开(公告)日：2013-08-20

申请号：US12949356

申请日：2010-11-18

申请人： Lianjun Liu ,  Chad S. Dawson ,  Bernhard H. Grote ,  Woo Tae Park

发明人： Lianjun Liu ,  Chad S. Dawson ,  Bernhard H. Grote ,  Woo Tae Park

IPC分类号： G01L9/06

CPC分类号： G01L9/0054 ,  G01L19/069

摘要： A pressure transducer includes a substrate, a piezoresistive element, a first conductive element, a first terminal, and a test structure. The substrate has a surface and a cavity. A diaphragm layer is formed over the cavity and over the surface of the substrate. The piezoresistive element is formed in the diaphragm layer. The first conductive element is formed in the diaphragm layer, and has a first conductivity type. The first conductive element is coupled to the piezoresistive element. The first terminal is formed over a surface of the diaphragm layer and coupled to the first conductive element. The test structure has the first conductivity type and is formed in the diaphragm layer. The test structure has an edge spaced apart from an edge of the first conductive element by a predetermined distance. A surface charge accumulation on the diaphragm layer is detected using the test structure.

摘要翻译： 压力传感器包括衬底，压阻元件，第一导电元件，第一端子和测试结构。 衬底具有表面和空腔。 在空腔上方和衬底的表面上形成隔膜层。 压电元件形成在隔膜层中。 第一导电元件形成在隔膜层中，并且具有第一导电类型。 第一导电元件耦合到压阻元件。 第一端子形成在隔膜层的表面上并且耦合到第一导电元件。 测试结构具有第一导电类型并形成在隔膜层中。 测试结构具有与第一导电元件的边缘间隔开预定距离的边缘。 使用测试结构来检测隔膜层上的表面电荷积聚。

公开(公告)号：US08338872B2

公开(公告)日：2012-12-25

申请号：US12750166

申请日：2010-03-30

申请人： Vishnu K. Khemka ,  Tahir A. Khan ,  Ronghua Zhu ,  Weixiao Huang ,  Bernhard H. Grote

发明人： Vishnu K. Khemka ,  Tahir A. Khan ,  Ronghua Zhu ,  Weixiao Huang ,  Bernhard H. Grote

IPC分类号： H01L29/66 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L27/0705 ,  H01L27/088 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.

摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。