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公开(公告)号:US20070004161A1
公开(公告)日:2007-01-04
申请号:US11516067
申请日:2006-09-06
Applicant: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
Inventor: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
IPC: H01L21/331
CPC classification number: H01L29/66242 , H01L21/8249 , H01L29/0817 , H01L29/36 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/7378
Abstract: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.
Abstract translation: 具有非常高动态性能的双极晶体管,可用于集成电路。 双极晶体管具有厚度小于50nm的单晶硅发射极区域。 双极晶体管的基极由SiGe合金制成。
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公开(公告)号:US20050037586A1
公开(公告)日:2005-02-17
申请号:US10838860
申请日:2004-05-03
Applicant: Michel Marty , Bertrand Martinet , Cyril Fellous
Inventor: Michel Marty , Bertrand Martinet , Cyril Fellous
IPC: H01L21/331 , H01L27/10
CPC classification number: H01L29/66287 , H01L29/66242
Abstract: A method for manufacturing a bipolar transistor, comprising the steps of: growing on the substrate a first semiconductor; depositing an encapsulation layer etchable with respect to the first semiconductor, forming a sacrificial block at the location of the base-emitter junction; exposing the first semiconductor around spacers formed around said block; forming a second semiconductor, then a third semiconductor etchable with respect to the second semiconductor layer, the encapsulation layer, and the spacers, the sum of the thicknesses of the second semiconductor and the sacrificial layer being substantially equal to the sum of the thicknesses of the encapsulation layer and of the sacrificial block; removing the block and the encapsulation layer; depositing a fourth semiconductor; removing the third semiconductor; and etching an insulating layer to maintain it on the emitter walls and between said emitter and the second semiconductor.
Abstract translation: 一种制造双极晶体管的方法,包括以下步骤:在衬底上生长第一半导体; 沉积相对于所述第一半导体可蚀刻的封装层,在所述基极 - 发射极结的位置处形成牺牲块; 将第一半导体暴露在围绕所述块形成的间隔件周围; 形成第二半导体,然后可蚀刻相对于第二半导体层,封装层和间隔物的第三半导体,第二半导体和牺牲层的厚度之和基本上等于 封装层和牺牲块; 去除块和封装层; 沉积第四半导体; 去除第三半导体; 并蚀刻绝缘层以将其保持在发射极壁上和所述发射极与第二半导体之间。
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公开(公告)号:US07824978B2
公开(公告)日:2010-11-02
申请号:US11516067
申请日:2006-09-06
Applicant: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
Inventor: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
IPC: H01L29/082
CPC classification number: H01L29/66242 , H01L21/8249 , H01L29/0817 , H01L29/36 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/7378
Abstract: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.
Abstract translation: 具有非常高动态性能的双极晶体管,可用于集成电路。 双极晶体管具有厚度小于50nm的单晶硅发射极区域。 双极晶体管的基极由SiGe合金制成。
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公开(公告)号:US07115465B2
公开(公告)日:2006-10-03
申请号:US10838860
申请日:2004-05-03
Applicant: Michel Marty , Bertrand Martinet , Cyril Fellous
Inventor: Michel Marty , Bertrand Martinet , Cyril Fellous
IPC: H01L21/8249
CPC classification number: H01L29/66287 , H01L29/66242
Abstract: A method for manufacturing a bipolar transistor, comprising the steps of: growing on the substrate a first semiconductor; depositing an encapsulation layer etchable with respect to the first semiconductor, forming a sacrificial block at the location of the base-emitter junction; exposing the first semiconductor around spacers formed around said block; forming a second semiconductor, then a third semiconductor etchable with respect to the second semiconductor layer, the encapsulation layer, and the spacers, the sum of the thicknesses of the second semiconductor and the sacrificial layer being substantially equal to the sum of the thicknesses of the encapsulation layer and of the sacrificial block; removing the block and the encapsulation layer; depositing a fourth semiconductor; removing the third semiconductor; and etching an insulating layer to maintain it on the emitter walls and between said emitter and the second semiconductor.
Abstract translation: 一种制造双极晶体管的方法,包括以下步骤:在衬底上生长第一半导体; 沉积相对于第一半导体可蚀刻的封装层,在基极 - 发射极结的位置处形成牺牲块; 将第一半导体暴露在围绕所述块形成的间隔件周围; 形成第二半导体,然后可蚀刻相对于第二半导体层,封装层和间隔物的第三半导体,第二半导体和牺牲层的厚度之和基本上等于 封装层和牺牲块; 去除块和封装层; 沉积第四半导体; 去除第三半导体; 并蚀刻绝缘层以将其保持在发射极壁上和所述发射极与第二半导体之间。
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公开(公告)号:US20060054998A1
公开(公告)日:2006-03-16
申请号:US10942165
申请日:2004-09-16
Applicant: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
Inventor: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
IPC: H01L27/082
CPC classification number: H01L29/66242 , H01L21/8249 , H01L29/0817 , H01L29/36 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/7378
Abstract: A novel bipolar transistor with very high dynamic performances, usable in an integrated circuit. This bipolar transistor comprises a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.
Abstract translation: 一种具有非常高动态性能的新型双极晶体管,可用于集成电路。 该双极晶体管包括厚度小于50nm的单晶硅发射极区域。 双极晶体管的基极由SiGe合金制成。
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公开(公告)号:US20050037587A1
公开(公告)日:2005-02-17
申请号:US10914482
申请日:2004-08-09
Applicant: Bertrand Martinet , Michel Marty , Pascal Chevalier , Alain Chantre
Inventor: Bertrand Martinet , Michel Marty , Pascal Chevalier , Alain Chantre
IPC: H01L21/331 , H01L29/08 , H01L21/8222
CPC classification number: H01L29/66287 , H01L29/0817 , H01L29/66242
Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.
Abstract translation: 一种用于形成异质结双极晶体管的方法,包括以下步骤:在半导体衬底中形成第一掺杂类型的集电极区域; 通过在集电区域的一部分上方的外延生长形成基区的第二掺杂类型的硅/锗层; 在硅/锗层之上形成由相对于硅/锗层可选择性地蚀刻的材料以及相对于层和连续形成的绝缘间隔物形成的牺牲发射体; 在所述牺牲发射体的侧面上形成第一绝缘间隔物; 通过将硅/锗层的暴露部分上的硅层外延生长; 形成与所述第一间隔物相邻的第二绝缘间隔物并铺设在所述硅层上; 用绝缘层覆盖整个结构; 部分去除牺牲发射体上方的绝缘层并去除牺牲发射极; 用第一掺杂类型的半导体材料填充先前由牺牲发射极占据的空间。
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7.
公开(公告)号:US07714390B2
公开(公告)日:2010-05-11
申请号:US11385044
申请日:2006-03-20
Applicant: Denis Cottin , Thierry Schwartzmann , Jean-Charles Vildeuil , Bertrand Martinet , Sophie Taupin , Mathieu Marin
Inventor: Denis Cottin , Thierry Schwartzmann , Jean-Charles Vildeuil , Bertrand Martinet , Sophie Taupin , Mathieu Marin
IPC: H01L23/62
CPC classification number: H01L27/0802 , H01L29/8605
Abstract: An integrated circuit includes a substrate and a resistor. The resistor is formed from at least two access wells of a first conductivity type and a deep buried layer electrically connecting the wells. The deep buried layer is at least partly covered by a region of opposite conductivity.
Abstract translation: 集成电路包括衬底和电阻器。 电阻器由至少两个第一导电类型的访问阱和电连接阱的深埋层形成。 深埋层至少部分地被相反电导率的区域覆盖。
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公开(公告)号:US07122879B2
公开(公告)日:2006-10-17
申请号:US10942165
申请日:2004-09-16
Applicant: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
Inventor: Alain Chantre , Bertrand Martinet , Michel Marty , Pascal Chevalier
CPC classification number: H01L29/66242 , H01L21/8249 , H01L29/0817 , H01L29/36 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/7378
Abstract: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.
Abstract translation: 具有非常高动态性能的双极晶体管,可用于集成电路。 双极晶体管具有厚度小于50nm的单晶硅发射极区域。 双极晶体管的基极由SiGe合金制成。
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9.
公开(公告)号:US20060226512A1
公开(公告)日:2006-10-12
申请号:US11385044
申请日:2006-03-20
Applicant: Denis Cottin , Thierry Schwartzmann , Jean-Charles Vildeuil , Bertrand Martinet , Sophie Taupin , Mathieu Marin
Inventor: Denis Cottin , Thierry Schwartzmann , Jean-Charles Vildeuil , Bertrand Martinet , Sophie Taupin , Mathieu Marin
IPC: H01L29/00
CPC classification number: H01L27/0802 , H01L29/8605
Abstract: An integrated circuit includes a substrate and a resistor. The resistor is formed from at least two access wells of a first conductivity type and a deep buried layer electrically connecting the wells. The deep buried layer is at least partly covered by a region of opposite conductivity.
Abstract translation: 集成电路包括基板和电阻器。 电阻器由至少两个第一导电类型的访问阱和电连接阱的深埋层形成。 深埋层至少部分地被相反电导率的区域覆盖。
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