Large scale IC personalization method employing air dielectric structure
for extended conductor
    2.
    发明授权
    Large scale IC personalization method employing air dielectric structure for extended conductor 失效
    使用扩展导体的空气电介质结构的大规模IC个性化方法

    公开(公告)号:US5530290A

    公开(公告)日:1996-06-25

    申请号:US226103

    申请日:1994-04-11

    摘要: Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

    摘要翻译: 用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。 壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。 壁图案也可以从一层开放,以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。 即使在大规模集成电路的单个器件层内,也可以获得宽范围的剪切强度和平均介电常数的降低,并被用于满足电路设计和器件制造工艺要求。

    Larce scale IC personalization method employing air dielectric structure
for extended conductors
    5.
    发明授权
    Larce scale IC personalization method employing air dielectric structure for extended conductors 失效
    Larce尺寸IC个性化方法采用空气电介质结构用于扩展导体

    公开(公告)号:US5444015A

    公开(公告)日:1995-08-22

    申请号:US225685

    申请日:1994-04-11

    摘要: Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

    摘要翻译: 用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。 壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。 壁图案也可以从一层开放,以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。 即使在大规模集成电路的单个器件层内,也可以获得宽范围的剪切强度和平均介电常数的降低,并被用于满足电路设计和器件制造工艺要求。

    Method of Fabricating a micro-coaxial wiring structure
    6.
    发明授权
    Method of Fabricating a micro-coaxial wiring structure 失效
    制造微同轴布线结构的方法

    公开(公告)号:US5363550A

    公开(公告)日:1994-11-15

    申请号:US996210

    申请日:1992-12-23

    IPC分类号: H01P3/06 H01B13/20

    摘要: A method of fabricating a micro-coaxial wiring structure comprises forming a first insulation layer and patterning a trench therein. A first conductive layer is formed on the first insulation layer and having a shape conforming to the insulation layer and lining the trench. A second insulation layer is formed on the first conductive layer within the trench and having a shape conforming to the first conductive layer lining the trench. A conductive signal line having a predetermined aspect ratio for providing a desired value of resistance per unit length is formed on the second insulation layer within the trench. A third insulation layer is then formed. Lastly, a conductive shielding line is formed upon the third insulation layer, the conductive shielding line being aligned with the conductive signal line.

    摘要翻译: 制造微同轴布线结构的方法包括形成第一绝缘层并在其中图案化沟槽。 第一导电层形成在第一绝缘层上并且具有与绝缘层一致的形状并衬在沟槽上。 第二绝缘层形成在沟槽内的第一导电层上,并且具有与衬套在沟槽上的第一导电层一致的形状。 在沟槽内的第二绝缘层上形成具有用于提供每单位长度的电阻值的预定宽高比的导电信号线。 然后形成第三绝缘层。 最后,在第三绝缘层上形成导电屏蔽线,导电屏蔽线与导电信号线对齐。