公开(公告)号：US09691459B2

公开(公告)日：2017-06-27

申请号：US15249845

申请日：2016-08-29

申请人： Bo-young Seo ,  Suk-soo Pyo ,  Gwan-hyeob Koh ,  Yong-kyu Lee ,  Dae-shik Kim

发明人： Bo-young Seo ,  Suk-soo Pyo ,  Gwan-hyeob Koh ,  Yong-kyu Lee ,  Dae-shik Kim

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/004 ,  G11C29/028 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2029/4402

摘要： A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

公开(公告)号：US20160163254A1

公开(公告)日：2016-06-09

申请号：US14957970

申请日：2015-12-03

申请人： Choong-jae Lee ,  Gwan-hyeob Koh ,  Dae-shik Kim ,  Bo-young Seo

发明人： Choong-jae Lee ,  Gwan-hyeob Koh ,  Dae-shik Kim ,  Bo-young Seo

IPC分类号： G09G3/20 ,  G06T1/60

CPC分类号： G06T1/60 ,  G06F12/00 ,  G06F12/0238 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/12 ,  G09G2360/18 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695

摘要： Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

摘要翻译： 提供了基于磁性随机存取存储器（MRAM）的帧缓冲装置，其可以通过使用像素自刷新（PSR）方法来减小其尺寸和功耗。 基于MRAM的帧缓冲装置包括包括磁随机存取存储器（MRAM）的帧缓冲存储器。 帧缓冲存储器存储至少一个帧数据。 基于MRAM的帧缓冲装置还包括被配置为检测外部磁场的磁场传感器; 以及帧缓冲器控制器，被配置为根据所检测的外部磁场的强度来控制所述至少一帧帧数据的存储。

公开(公告)号：US20140269064A1

公开(公告)日：2014-09-18

申请号：US14208200

申请日：2014-03-13

申请人： Chang-Min Jeon ,  Bo-Young Seo ,  Tea-Kwang Yu

发明人： Chang-Min Jeon ,  Bo-Young Seo ,  Tea-Kwang Yu

IPC分类号： G11C16/24 ,  G11C16/26

CPC分类号： G11C16/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C16/08 ,  G11C16/26 ,  G11C2213/79 ,  G11C2213/82

摘要： A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described.

摘要翻译： 源极线浮置电路包括多个浮动单元。 浮动单元分别直接接收解码的行地址信号或字线的电压作为浮动控制信号。 解码的行地址信号响应于行地址信号被选择性地激活。 浮动单元响应于读操作中的浮动控制信号来控制源线之间的电连接和源极电压。 还描述了相关的装置和方法。

公开(公告)号：US08476130B2

公开(公告)日：2013-07-02

申请号：US13180613

申请日：2011-07-12

申请人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

IPC分类号： H01L21/8238

CPC分类号： H01L27/2436 ,  H01L27/105 ,  H01L27/2445 ,  H01L45/1683

摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.

摘要翻译： 一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

公开(公告)号：US20120087189A1

公开(公告)日：2012-04-12

申请号：US13177873

申请日：2011-07-07

申请人： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

发明人： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

摘要： A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

摘要翻译： 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

公开(公告)号：US07697336B2

公开(公告)日：2010-04-13

申请号：US11903482

申请日：2007-09-21

申请人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

发明人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

摘要翻译： 本发明涉及一种非易失性存储器件及其操作方法。 非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。 第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。 非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。 由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。

公开(公告)号：US07696561B2

公开(公告)日：2010-04-13

申请号：US11870762

申请日：2007-10-11

申请人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

发明人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

摘要翻译： 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。

公开(公告)号：US07521750B2

公开(公告)日：2009-04-21

申请号：US12017239

申请日：2008-01-21

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

IPC分类号： H01L29/76

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5692 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile semiconductor device includes a pair of multi-bit nonvolatile memory unit cells. Each unit cell includes a grid type semiconductor body in which a plurality of parallel semiconductor bodies extend in a first direction and a plurality of parallel semiconductor bodies extend in a second direction perpendicular to the first direction, a channel region formed in a partial region of the semiconductor body along circumferences of the semiconductor bodies that extend in the first direction, a charge storage region formed on the channel region, a plurality of control gates, which are formed on the charge storage region and wherein each of the plurality of control gates is adapted to receive separate control voltages. Each unit cell further includes source and drain regions aligned on both sides of the plurality of control gates and formed in the semiconductor bodies, wherein the pair of unit cells share the source region, and the source region is formed at a cross point of the grid.

摘要翻译： 非易失性半导体器件包括一对多位非易失性存储单元。 每个单电池包括栅格型半导体本体，其中多个平行的半导体本体在第一方向上延伸，并且多个平行的半导体本体在垂直于第一方向的第二方向上延伸，沟道区形成在 半导体本体沿着在第一方向上延伸的半导体本体的周边，形成在沟道区上的电荷存储区域，形成在电荷存储区域上的多个控制栅极，并且其中多个控制栅极中的每一个被适配 以接收单独的控制电压。 每个单元还包括在多个控制栅极的两侧对准并形成在半导体主体中的源极和漏极区域，其中该对单元电池共享源极区域，并且源极区域形成在栅极的交叉点处 。

公开(公告)号：US07512003B2

公开(公告)日：2009-03-31

申请号：US11789003

申请日：2007-04-23

申请人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

发明人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

摘要翻译： 非易失性存储器件包括存储器单元块，第一切换块和第二切换块。 多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管 它连接到源线。 第一切换块选择性地将全局位线连接到本地位线，而第二切换块以预定位数为单位来控制存储单元块中的存储单元。 第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

公开(公告)号：US20080253190A1

公开(公告)日：2008-10-16

申请号：US11903482

申请日：2007-09-21

申请人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

发明人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

摘要翻译： 本发明涉及一种非易失性存储器件及其操作方法。 非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。 第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。 非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。 由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。