公开(公告)号：US08853035B2

公开(公告)日：2014-10-07

申请号：US13253375

申请日：2011-10-05

申请人： Xiaojun Yu ,  Brian J. Greene ,  Yue Liang

发明人： Xiaojun Yu ,  Brian J. Greene ,  Yue Liang

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/28

CPC分类号： H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

摘要： In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

摘要翻译： 在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构 。 嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。 半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。 还提供了形成上述装置的方法。

公开(公告)号：US08513085B2

公开(公告)日：2013-08-20

申请号：US13409693

申请日：2012-03-01

申请人： Sunfei Fang ,  Brian J. Greene ,  Effendi Leobandung ,  Qingqing Liang ,  Edward P. Maciejewski ,  Yanfeng Wang

发明人： Sunfei Fang ,  Brian J. Greene ,  Effendi Leobandung ,  Qingqing Liang ,  Edward P. Maciejewski ,  Yanfeng Wang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636

摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

摘要翻译： 提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。 含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

公开(公告)号：US08466496B2

公开(公告)日：2013-06-18

申请号：US13298783

申请日：2011-11-17

申请人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

发明人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823871 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

摘要翻译： 互补金属氧化物半导体（CMOS）器件，其可以包括具有通过隔离区彼此分离的第一有源区和第二有源区的衬底。 在第一有源区上存在n型半导体器件，其包括具有第一栅极介电层和n型功函数金属层的第一栅极结构，其中n型功函数层不延伸到隔离区 。 p型半导体器件存在于第二有源区，其包括具有第二栅极介电层和p型功函数金属层的第二栅极结构，其中p型功函数层不延伸到隔离区 。 连接栅极结构跨越隔离区域延伸成与第一栅极结构和第二栅极结构直接接触。

公开(公告)号：US20130099313A1

公开(公告)日：2013-04-25

申请号：US13276395

申请日：2011-10-19

申请人： Eduard A. CARTIER ,  Brian J. GREENE ,  Dechao GUO ,  Gan WANG ,  Yanfeng WANG ,  Keith Kwong Hon WONG

发明人： Eduard A. CARTIER ,  Brian J. GREENE ,  Dechao GUO ,  Gan WANG ,  Yanfeng WANG ,  Keith Kwong Hon WONG

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/785 ,  H01L21/02323 ,  H01L21/28017 ,  H01L27/1211 ,  H01L29/6656 ,  H01L29/66795

摘要： FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

公开(公告)号：US20120139081A1

公开(公告)日：2012-06-07

申请号：US13370898

申请日：2012-02-10

申请人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

公开(公告)号：US08115254B2

公开(公告)日：2012-02-14

申请号：US11860851

申请日：2007-09-25

申请人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

IPC分类号： H01L27/12

CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

公开(公告)号：US08030687B2

公开(公告)日：2011-10-04

申请号：US11764948

申请日：2007-06-19

申请人： Alberto Escobar ,  Brian J. Greene ,  Edward J. Nowak

发明人： Alberto Escobar ,  Brian J. Greene ,  Edward J. Nowak

IPC分类号： H01L29/84 ,  H01L21/338

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L29/66575 ,  H01L29/7849

摘要： Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

摘要翻译： 公开了具有降低的驱动电流温度灵敏度的场效应晶体管（FET）的实施例。 具体地说，通过与应变相关的载流子迁移率变化相反的FET通道区域中任何温度依赖的载流子迁移率变化被同时抵消，以确保驱动电流响应于温度变化保持近似恒定或至少在预定范围内。 这种相反的应变依赖性载流子迁移率变化由应变结构提供，该应变结构被配置为在通道区域上赋予预选的应变类型的温度相关量。 还公开了形成场效应晶体管的相关方法的实施例。

公开(公告)号：US20110031554A1

公开(公告)日：2011-02-10

申请号：US12535183

申请日：2009-08-04

申请人： Sunfei Fang ,  Brian J. Greene ,  Effendi Leobandung ,  Qingqing Liang ,  Edward P. Maciejewski ,  Yanfeng Wang

发明人： Sunfei Fang ,  Brian J. Greene ,  Effendi Leobandung ,  Qingqing Liang ,  Edward P. Maciejewski ,  Yanfeng Wang

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636

摘要： A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

摘要翻译： 提供了形成阈值电压控制的半导体结构的方法，其中在至少暴露的具有大于氧化硅的介电常数的栅极介电材料的侧壁上形成共形氮化物衬里。 含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

公开(公告)号：US07790553B2

公开(公告)日：2010-09-07

申请号：US12170687

申请日：2008-07-10

申请人： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

发明人： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/82385 ,  H01L21/823857

摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

摘要翻译： 公开了在MOSFET中形成高性能栅极的方法及其结构。 一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。 以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET， 第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

公开(公告)号：US07759739B2

公开(公告)日：2010-07-20

申请号：US11163683

申请日：2005-10-27

申请人： Dureseti Chidambarrao ,  Brian J. Greene ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Brian J. Greene ,  Kern Rim

IPC分类号： H01L29/94

CPC分类号： H01L21/823481 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/0653 ,  H01L29/7846

摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.

摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 具有水平延伸的上表面的介电应激元件在有源半导体区域的一部分的下方延伸。 电介质应力元件与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。 在特定结构中，在FET的纵向和/或横向方向上彼此相对的位置处提供两个或更多个介电应激元件。