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    User-configurable high-speed line driver
    1.
    发明授权
    User-configurable high-speed line driver 有权

    公开(公告)号：US12206530B2

    公开(公告)日：2025-01-21

    申请号：US18151171

    申请日：2023-01-06

    Applicant: Brookhaven Science Associates, LLC

    Inventor： Grzegorz W. Deptuch ,  Nicholas Benjamin St. John ,  Soumyajit Mandal

    IPC: H04L25/03 ,  H04L7/033

    Abstract: An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

    High-bandwidth reconfigurable data acquisition card
    9.
    发明授权
    High-bandwidth reconfigurable data acquisition card 有权

    公开(公告)号：US11816053B2

    公开(公告)日：2023-11-14

    申请号：US17428810

    申请日：2019-09-23

    Applicant: Brookhaven Science Associates, LLC

    Inventor： Kai Chen ,  Michael Begel ,  Hucheng Chen ,  Francesco Lanni

    IPC: G06F13/40 ,  H03K19/14 ,  H04B10/40 ,  H04J3/06

    CPC classification number: G06F13/4022 ,  H03K19/14 ,  H04B10/40 ,  H04J3/0685

    Abstract: A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

    FORMATION OF ANTIREFLECTIVE SURFACES
    10.
    发明申请
    FORMATION OF ANTIREFLECTIVE SURFACES 有权

    公开(公告)号：US20220402754A1

    公开(公告)日：2022-12-22

    申请号：US17858855

    申请日：2022-07-06

    Applicant: Brookhaven Science Associates LLC

    Inventor： Charles T. Black ,  Atikur Rahman ,  Matthew Eisaman ,  Ahsan Ashraf

    IPC: B81C1/00 ,  B82Y30/00 ,  H01L31/0236 ,  G02B1/118 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308

    Abstract: Methods for etching nanostructures in a substrate include depositing a patterned block copolymer on the substrate, the patterned block copolymer including first and second polymer block domains, applying a precursor to the patterned block copolymer to generate an infiltrated block copolymer, the precursor infiltrating into the first polymer block domain and generating a material in the first polymer block domain, applying a removal agent to the infiltrated block copolymer to generate a patterned material, the removal agent removing the first and second polymer block domains from the substrate, and etching the substrate, the patterned material on the substrate masking the substrate to pattern the etching. The etching may be performed under conditions to produce nanostructures in the substrate.

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