公开(公告)号：US07501863B2

公开(公告)日：2009-03-10

申请号：US11724128

申请日：2007-03-14

申请人： Bruce Querbach ,  Randall B. Hamilton ,  Luke A. Johnson ,  Minyoung Kim

发明人： Bruce Querbach ,  Randall B. Hamilton ,  Luke A. Johnson ,  Minyoung Kim

IPC分类号： H03K17/00

CPC分类号： H03F3/005

摘要： A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

摘要翻译： 开关电容电路可用于均衡，但可配置为电压裕度。 开关电容电路消除放大器固有的偏移电压，并将输入信号的共模设置为轨电压的一半。 在施加到放大器的两个输入端口之前，两个电容器将输入信号电平移位。 当用于电压裕度时，通过将数模转换控制电压源连接到两个电容器，在放大器的输入端口输入电压摆幅减小。

公开(公告)号：US07228515B2

公开(公告)日：2007-06-05

申请号：US10846721

申请日：2004-05-13

申请人： Bruce Querbach ,  Amjad Khan ,  Mike Tripp ,  Luis Briceno Guerrero ,  Marco A. Vindas Vargas ,  Ali Muhtaroglu

发明人： Bruce Querbach ,  Amjad Khan ,  Mike Tripp ,  Luis Briceno Guerrero ,  Marco A. Vindas Vargas ,  Ali Muhtaroglu

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

摘要翻译： 本发明的实施例提供了一种具有其中实现的可控延迟模型的逻辑仿真，其可用于通过引入允许逻辑模拟器来模拟模拟行为的延迟模型来验证硅前置环境中的AC I / O环回设计。 对于本发明的一个实施例，选择固定的处理器比率，硬件描述语言的延迟语句对应于特定的时间延迟。 这些固定值提供了准确确定和调整模拟仿真延迟的能力。

公开(公告)号：US10198333B2

公开(公告)日：2019-02-05

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

公开(公告)号：US20110161752A1

公开(公告)日：2011-06-30

申请号：US12651252

申请日：2009-12-31

申请人： BRYAN L. SPRY ,  THEODORE Z. SCHOENBORN ,  PHILIP ABRAHAM ,  CHRISTOPHER P. MOZAK ,  DAVID G. ELLIS ,  JAY J. NEJEDLO ,  BRUCE QUERBACH ,  ZVIKA GREENFIELD ,  RONY GHATTAS ,  JAYASEKHAR THOLIYIL ,  CHARLES D. LUCAS ,  CHRISTOPHER E. YUNKER

发明人： BRYAN L. SPRY ,  THEODORE Z. SCHOENBORN ,  PHILIP ABRAHAM ,  CHRISTOPHER P. MOZAK ,  DAVID G. ELLIS ,  JAY J. NEJEDLO ,  BRUCE QUERBACH ,  ZVIKA GREENFIELD ,  RONY GHATTAS ,  JAYASEKHAR THOLIYIL ,  CHARLES D. LUCAS ,  CHRISTOPHER E. YUNKER

IPC分类号： G11C29/04 ,  G06F11/22 ,  G06F12/08 ,  G06F12/02

CPC分类号： G11C29/08 ,  G11C29/10 ,  G11C29/44

摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。

公开(公告)号：US20080231356A1

公开(公告)日：2008-09-25

申请号：US11724128

申请日：2007-03-14

申请人： Bruce Querbach ,  Randall B. Hamilton ,  Luke A. Johnson ,  Minyoung Kim

发明人： Bruce Querbach ,  Randall B. Hamilton ,  Luke A. Johnson ,  Minyoung Kim

IPC分类号： H03F1/02

CPC分类号： H03F3/005

摘要： A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

摘要翻译： 开关电容电路可用于均衡，但可配置为电压裕度。 开关电容电路消除放大器固有的偏移电压，并将输入信号的共模设置为轨电压的一半。 在施加到放大器的两个输入端口之前，两个电容器将输入信号电平移位。 当用于电压裕度时，通过将数模转换控制电压源连接到两个电容器，在放大器的输入端口输入电压摆幅减小。

公开(公告)号：US20060265161A1

公开(公告)日：2006-11-23

申请号：US11124553

申请日：2005-05-06

申请人： Bruce Querbach ,  Mohammad Abdallah ,  Amjad Khan ,  Mir Hossain ,  Sanjib Sarkar

发明人： Bruce Querbach ,  Mohammad Abdallah ,  Amjad Khan ,  Mir Hossain ,  Sanjib Sarkar

IPC分类号： G06F19/00

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037

摘要： A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

公开(公告)号：US20050257185A1

公开(公告)日：2005-11-17

申请号：US10846721

申请日：2004-05-13

申请人： Bruce Querbach ,  Amjad Khan ,  Mike Tripp ,  Luis Guerrero ,  Marco Vindas Vargas ,  Ali Muhtaroglu

发明人： Bruce Querbach ,  Amjad Khan ,  Mike Tripp ,  Luis Guerrero ,  Marco Vindas Vargas ,  Ali Muhtaroglu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

摘要翻译： 本发明的实施例提供了一种具有其中实现的可控延迟模型的逻辑仿真，其可用于通过引入允许逻辑模拟器来模拟模拟行为的延迟模型来验证硅前置环境中的AC I / O环回设计。 对于本发明的一个实施例，选择固定的处理器比率，硬件描述语言的延迟语句对应于特定的时间延迟。 这些固定值提供了准确确定和调整模拟仿真延迟的能力。

公开(公告)号：US20150187439A1

公开(公告)日：2015-07-02

申请号：US14141239

申请日：2013-12-26

申请人： Bruce Querbach ,  Theodore Z. Schoenborn ,  David J. Zimmerman ,  David G. Ellis ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang ,  Ramakrishna Mallela ,  William K. Lui

发明人： Bruce Querbach ,  Theodore Z. Schoenborn ,  David J. Zimmerman ,  David G. Ellis ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang ,  Ramakrishna Mallela ,  William K. Lui

IPC分类号： G11C29/36 ,  G06F11/263

CPC分类号： G11C29/36 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C2029/4402

摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. Other aspects are described herein.

摘要翻译： 根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。 在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。 在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储单元。 本文描述了其它方面。

公开(公告)号：US20150127983A1

公开(公告)日：2015-05-07

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273

CPC分类号： G06F11/2733 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

公开(公告)号：US08868992B2

公开(公告)日：2014-10-21

申请号：US12651252

申请日：2009-12-31

申请人： Bryan L. Spry ,  Theodore Z. Schoenborn ,  Philip Abraham ,  Christopher P. Mozak ,  David G. Ellis ,  Jay J. Nejedlo ,  Bruce Querbach ,  Zvika Greenfield ,  Rony Ghattas ,  Jayasekhar Tholiyil ,  Charles D. Lucas ,  Christopher E. Yunker

发明人： Bryan L. Spry ,  Theodore Z. Schoenborn ,  Philip Abraham ,  Christopher P. Mozak ,  David G. Ellis ,  Jay J. Nejedlo ,  Bruce Querbach ,  Zvika Greenfield ,  Rony Ghattas ,  Jayasekhar Tholiyil ,  Charles D. Lucas ,  Christopher E. Yunker

IPC分类号： G06F11/00 ,  G11C29/08

CPC分类号： G11C29/08 ,  G11C29/10 ,  G11C29/44

摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。