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1.发明授权Utilization-aware low-overhead link-width modulation for power reduction in interconnects 有权利用率低的架空链路宽度调制，用于互连中的功率降低公开(公告)号：US09053244B2
公开(公告)日：2015-06-09
申请号：US13536852
申请日：2012-06-28
申请人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
发明人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
CPC分类号： G06F13/4027 , G06F1/3203 , G06F1/3253 , G06F13/4018 , G06F13/4221 , G06F15/16 , Y02D10/151
摘要： Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。 在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。 更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。 还公开并要求保护其他实施例。
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2.发明授权Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders 失效使用4位乘4位乘法器和级联加法器的快速n位乘n位乘法器
公开(公告)号：US5912832A
公开(公告)日：1999-06-15
申请号：US713822
申请日：1996-09-12
申请人： Michael F. Flahie , Buck W. Gremel
发明人： Michael F. Flahie , Buck W. Gremel
CPC分类号： G06F7/5324 , G06F7/505
摘要： A method and apparatus for n-bit by n-bit multiplication is disclosed using paralleled 4-bit by 4-bit multipliers and cascaded adder structures. The cascaded adder structures may be used to produce non-pipelined, integer, n-bit by n-bit multipliers with higher throughput than systolic array multipliers of similar geometries.
摘要翻译： 使用并行的4位乘4位乘法器和级联加法器结构公开了用于n位乘以n位的方法和装置。 级联加法器结构可以用于产生具有比具有相似几何形状的收缩阵列乘法器更高吞吐量的非流水线，整数，n位乘以n比特乘法器。
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公开(公告)号：US20140095944A1
公开(公告)日：2014-04-03
申请号：US13631934
申请日：2012-09-29
CPC分类号： G06F1/3253 , Y02D10/151
摘要： An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
摘要翻译： 公开了一种用于优化在基于处理器的系统内操作的链路的等待时间和功率的装置和方法。 该装置和方法包括内置于不依赖于队列深度阈值的队列中的等待时间计。 该装置和方法还包括反馈逻辑，其优化围绕增加的延迟目标的功率降低以对由链路的物理属性施加的缓慢的重新供应行为作出反应。
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公开(公告)号：US20160147280A1
公开(公告)日：2016-05-26
申请号：US14554585
申请日：2014-11-26
申请人： Tessil Thomas , Lokesh Sharma , Buck W. Gremel , Ian M. Steiner
发明人： Tessil Thomas , Lokesh Sharma , Buck W. Gremel , Ian M. Steiner
CPC分类号： G06F1/206 , G06F1/3243 , Y02D10/152 , Y02D10/16
摘要： In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括执行指令的至少一个核心，与所述至少一个核心相关联的一个或多个热传感器以及耦合到所述至少一个核心的功率控制器。 功率控制器具有用于接收关于处理器的温度信息的控制逻辑，并且至少部分地基于温度信息动态地确定最大允许平均功率限制。 控制逻辑可以进一步保持处理器的静态最大基本操作频率，而不管温度信息的值。 描述和要求保护其他实施例。
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5.发明申请UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS 有权用于互连中功率降低的应用 - 低电平连接宽度调节公开(公告)号：US20140006673A1
公开(公告)日：2014-01-02
申请号：US13536852
申请日：2012-06-28
申请人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
发明人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F1/3203 , G06F1/3253 , G06F13/4018 , G06F13/4221 , G06F15/16 , Y02D10/151
摘要： Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。 在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。 更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。 还公开并要求保护其他实施例。
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6.发明授权Method for signaling PCI/PCI-X standard hot-plug controller (SHPC) command status 有权信号PCI / PCI-X标准热插拔控制器（SHPC）命令状态的方法公开(公告)号：US07257659B2
公开(公告)日：2007-08-14
申请号：US10750338
申请日：2003-12-31
申请人： Peter N. Martin , Buck W. Gremel
发明人： Peter N. Martin , Buck W. Gremel
CPC分类号： G06F13/385
摘要： According to embodiments of the present invention, indicators on a PCI/PCI-X controlled by a Standard Hot-Plug Controller (SHPC) have non-fifty percent duty cycle blinking patterns that communicate to an operator a particular command being processed, whether the command was processed successfully, whether a “hard” or “soft” error occurred if the command was processed successfully, and whether power was applied to the slot if the command was not processed successfully.
摘要翻译： 根据本发明的实施例，由标准热插拔控制器（SHPC）控制的PCI / PCI-X上的指示器具有非50％占空比的闪烁模式，其向操作者通信正在处理的特定命令，无论命令 被成功处理，如果命令成功处理，是否发生“硬”或“软”错误，以及如果命令未成功处理，是否将电源应用于插槽。
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