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    CMOS devices with different metals in gate electrodes using spin on low-k material as hard mask
    5.
    发明授权
    CMOS devices with different metals in gate electrodes using spin on low-k material as hard mask 有权
    具有不同金属的CMOS器件，在栅极上使用低k材料作为硬掩模

    公开(公告)号：US07943453B2

    公开(公告)日：2011-05-17

    申请号：US11960881

    申请日：2007-12-20

    申请人： Bernd Ernst Eduard Kastenmeier ,  Byoung Hun Lee ,  Naim Moumen ,  Theodorus Eduardus Standaert

    发明人： Bernd Ernst Eduard Kastenmeier ,  Byoung Hun Lee ,  Naim Moumen ,  Theodorus Eduardus Standaert

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L27/092

    摘要： A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

    摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底，在半导体衬底的顶部上的栅极电介质层。 该结构还包括位于栅介质层顶部的第一金属容纳区域。 该结构还包括在栅极电介质层的顶部上的第二金属容纳区域，其中第一和第二金属容纳区域彼此直接物理接触。 该结构还包括在第一和第二金属容纳区域的顶部上的栅极电极层，并且栅电极层与第一和第二金属容纳区域直接物理接触。 该结构还包括在栅极电极层的顶部上的图案化光致抗蚀剂层。

    CMOS DEVICES WITH DIFFERENT METALS IN GATE ELECTRODES USING SPIN ON LOW-K MATERIAL AS HARD MASK
    6.
    发明申请
    CMOS DEVICES WITH DIFFERENT METALS IN GATE ELECTRODES USING SPIN ON LOW-K MATERIAL AS HARD MASK 有权
    使用低K材料作为硬掩模旋转的门电极中具有不同金属的CMOS器件

    公开(公告)号：US20090159991A1

    公开(公告)日：2009-06-25

    申请号：US11960881

    申请日：2007-12-20

    申请人： Bernd Ernst Eduard Kastenmeier ,  Byoung Hun Lee ,  Naim Moumen ,  Theodorus Eduardus Standaert

    发明人： Bernd Ernst Eduard Kastenmeier ,  Byoung Hun Lee ,  Naim Moumen ,  Theodorus Eduardus Standaert

    IPC分类号： H01L29/78 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L27/092

    摘要： A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

    摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底，在半导体衬底的顶部上的栅极电介质层。 该结构还包括位于栅介质层顶部的第一金属容纳区域。 该结构还包括在栅极电介质层的顶部上的第二金属容纳区域，其中第一和第二金属容纳区域彼此直接物理接触。 该结构还包括在第一和第二金属容纳区域的顶部上的栅极电极层，并且栅电极层与第一和第二金属容纳区域直接物理接触。 该结构还包括在栅极电极层的顶部上的图案化光致抗蚀剂层。

    Methods for measuring capacitance
    7.
    发明授权
    Methods for measuring capacitance 失效
    测量电容的方法

    公开(公告)号：US07548067B2

    公开(公告)日：2009-06-16

    申请号：US11552779

    申请日：2006-10-25

    申请人： Kin P. Cheung ,  Dawei Heh ,  Byoung Hun Lee ,  Rino Choi

    发明人： Kin P. Cheung ,  Dawei Heh ,  Byoung Hun Lee ,  Rino Choi

    IPC分类号： G01R31/11 ,  G01R27/04 ,  G01R27/32 ,  G01R31/26

    CPC分类号： G01R27/2605 ,  G01R31/2831

    摘要： Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.

    摘要翻译： 提供了确定半导体（MOS）结构上的金属的电容值的方法。 时域反射测量电路可以装载MOS结构。 MOS结构可能被各种电压偏置，并且可以收集来自施加的电压的反射波形。 可以根据反射波形来确定MOS结构的电容。

    Chemical mechanical polishing (CMP) apparatus and CMP method using the same
    9.
    发明授权
    Chemical mechanical polishing (CMP) apparatus and CMP method using the same 失效
    化学机械抛光（CMP）装置和使用其的CMP方法

    公开(公告)号：US5837610A

    公开(公告)日：1998-11-17

    申请号：US805659

    申请日：1997-02-27

    申请人： Byoung-hun Lee ,  Joon-hee Lee

    发明人： Byoung-hun Lee ,  Joon-hee Lee

    IPC分类号： B24B1/00 ,  B24B37/00 ,  B24B37/20 ,  B24B37/24 ,  B24B57/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105

    CPC分类号： B24B57/02 ,  B24B37/04 ,  H01L21/31051

    摘要： A chemical mechanical polishing (CMP) apparatus for planarizing a semiconductor wafer includes a wafer carrier for loading and fixing a semiconductor wafer to be polished and a polishing platen rotating at a constant speed, disposed at a lower portion of the wafer carrier. A polishing pad is provided on an upper surface of the polishing platen, and is in contact with a surface of the semiconductor wafer. A spiral slurry feed line supplies a slurry solution to the polishing pad. An end of the spiral slurry feed line is provided with a plurality of nozzles and the spiral slurry feed line is connected to a deionized water feed line that is opened or closed by a valve. Accordingly, abrasives are prevented from being precipitated, and the slurry solution is uniformly supplied to the semiconductor wafer, to thereby enhance polishing uniformity.

    摘要翻译： 用于平坦化半导体晶片的化学机械抛光（CMP）装置包括用于加载和固定待抛光的半导体晶片的晶片载体和设置在晶片载体的下部的以恒定速度旋转的研磨平板。 抛光垫设置在研磨台板的上表面上并与半导体晶片的表面接触。 螺旋浆料进料管线将浆液提供给抛光垫。 螺旋浆料供给管线的端部设置有多个喷嘴，并且螺旋浆料进料管线连接到由阀打开或关闭的去离子水进料管线。 因此，防止了研磨剂的沉淀，将浆液溶液均匀地供给到半导体晶片，从而提高了研磨均匀性。

    Wafer polishing device
    10.
    发明授权
    Wafer polishing device 失效
    晶圆抛光装置

    公开(公告)号：US5735731A

    公开(公告)日：1998-04-07

    申请号：US606194

    申请日：1996-02-23

    申请人： Byoung-hun Lee

    发明人： Byoung-hun Lee

    IPC分类号： B24B37/20 ,  B24B37/22 ,  B24D9/00 ,  H01L21/304 ,  H01L21/683 ,  B24B5/00

    CPC分类号： B24B37/22 ,  B24B37/26 ,  B24D13/12 ,  B24D9/00

    摘要： An improved chemical mechanical polishing (CMP) device for chemically and mechanically planarizing the surface of a semiconductor wafer includes a flat wafer stage for loading and affixation of the semiconductor wafer so that the surface of a material to be polished, i.e. the surface of the wafer, faces up, and a cylindrical polishing pad formed above the exposed surface of the wafer to be polished which is rotatable at high speed so that the contact point of the wafer and the pad moves linearly. The stage is constructed to support a wafer by a vacuum suction through vacuum holes. The cylindrical polishing pad has a rotating axis for transmitting rotation at the center, thereof, and a double layer polishing pad having different hardness on a peripheral surface of the rotating axis.

    摘要翻译： 用于化学和机械平面化半导体晶片的表面的改进的化学机械抛光（CMP）装置包括用于加载和固定半导体晶片的平坦晶片台，使得待抛光材料的表面，即晶片的表面 面朝上，以及形成在要被抛光的晶片的暴露表面上的高速旋转的圆柱形抛光垫，使得晶片和衬垫的接触点线性移动。 该台被构造成通过真空孔通过真空抽吸来支撑晶片。 圆筒形抛光垫具有用于在其中心传递旋转的旋转轴线和在旋转轴的圆周表面上具有不同硬度的双层抛光垫。