公开(公告)号：US12237384B2

公开(公告)日：2025-02-25

申请号：US17515806

申请日：2021-11-01

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： ChihCheng Liu

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45

Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a gate structure and a self-aligned contact structure. The substrate includes a source region and a drain region; the gate structure is formed on the substrate and are located between the source region and the drain region; and the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure sequentially connected in a direction perpendicular to the substrate, the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate.

公开(公告)号：US12237042B2

公开(公告)日：2025-02-25

申请号：US17952394

申请日：2022-09-26

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Feng Lin

IPC: G11C7/10 ,  G11C7/22 ,  H03F3/45 ,  G11C7/02

Abstract: Provided is data receiving circuit, data receiving system and memory device. The data receiving circuit includes: first amplification circuit, configured to receive data signal, first reference signal and second reference signal, perform first comparison on the data signal and the first reference signal in response to sampling clock signal and output first signal pair, and perform second comparison on the data signal and the second reference signal and output second signal pair; second amplification circuit, configured to receive enable signal and feedback signal, selectively receive the first signal pair or the second signal pair as input signal pair based on the feedback signal during period in which the enable signal is at first level, receive the first signal pair during period in which the enable signal is at second level, amplify voltage difference of the first signal pair, and output first output signal and second output signal.

公开(公告)号：US12237038B2

公开(公告)日：2025-02-25

申请号：US17867687

申请日：2022-07-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Weibing Shang

IPC: G11C7/06 ,  G11C7/22

Abstract: A local sensing amplifier and a memory are provided. The local sensing amplifier is connected to a global signal line and is connected to a sense amplifier array by means of a local signal line and a complementary local signal line. The local sensing amplifier transmits a signal on the local signal line to the global signal line when a read control signal is received, and to transmit a signal on the global signal line to the local signal line when a write control signal is received. The local sensing amplifier includes a precharge circuit connected to a preset voltage source, the local signal line and the complementary local signal line. The preset voltage source provides a first voltage in a read-write interval and provide a second voltage in an idle period. The precharge circuit transmits first voltage to the local signal line and the complementary local signal line.

公开(公告)号：US12230668B2

公开(公告)日：2025-02-18

申请号：US17452644

申请日：2021-10-28

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yonghao Du

IPC: H01L49/02

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided. A lower electrode is formed on the substrate. A capacitor dielectric layer is formed on a surface of the lower electrode. The capacitor dielectric layer includes at least one zirconium oxide layer. The capacitor dielectric layer is subjected with microwave annealing treatment to convert a crystal phase of zirconium oxide to a tetragonal crystal phase. An upper electrode is formed on a surface of the capacitor dielectric layer.

公开(公告)号：US12230348B2

公开(公告)日：2025-02-18

申请号：US18155124

申请日：2023-01-17

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yoonjoo Eom ,  Lin Wang ,  Zhiqiang Zhang ,  Yuanyuan Gong

IPC: G11C29/14 ,  G11C29/36 ,  G11C29/46

Abstract: Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.

公开(公告)号：US12230339B2

公开(公告)日：2025-02-18

申请号：US18036036

申请日：2022-07-12

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Sungsoo Chi

IPC: G11C17/16 ,  G11C7/08 ,  G11C17/18

Abstract: The present disclosure provides an electronic device and a driving method. The electronic device comprises: a sensitivity amplifier and a voltage adjustment circuit. The sensitivity amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The control circuit is connected to the third node, the fourth node, and a preset voltage terminal. A first control signal terminal responds to the signal of the first control signal terminal to connect the preset voltage terminal and the third node and the fourth node. The preset voltage terminal inputs a preset voltage signal. The electronic device write a preset voltage signal of a suitable size to the sensitivity amplifier through the voltage adjustment circuit, so that the sensitivity amplifier has an appropriate voltage difference between the bit line and the complementary bit line during offset elimination.

公开(公告)号：US12225712B2

公开(公告)日：2025-02-11

申请号：US17453875

申请日：2021-11-08

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Gongyi Wu ,  Xiaoling Wang

IPC: H10B12/00

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple initial active pillars on the substrate; forming a gate layer between initial active pillars; and forming a first dielectric layer with openings on the gate layer and on the initial active pillars; removing part of the initial active pillar located in each opening to form an active pillar; and removing part of the gate layer to form an isolation trench and a word line, such that two adjacent active pillars in the same row are located on two sides of the isolation trench.

公开(公告)号：US12224280B2

公开(公告)日：2025-02-11

申请号：US17376112

申请日：2021-07-14

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Qian Xu

IPC: H01L27/02 ,  H02H9/04 ,  H03K17/081

Abstract: An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

公开(公告)号：US12222385B2

公开(公告)日：2025-02-11

申请号：US17445946

申请日：2021-08-25

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yu-Ting Cheng

IPC: G01R31/28

Abstract: A testing method includes: a wafer under test is detected based on a pre-set test region to obtain detection results of a plurality of chips in the wafer under test; a discrete point distribution diagram of the detection results of the plurality of chips are obtained, a discrete point in the discrete point distribution diagram being used for representing a position of an abnormal chip in the wafer under test; the discrete point distribution diagram is divided into a plurality of test regions based on graphic distribution characteristics in the pre-set test region, and a test result distribution diagram for representing graphic characteristics of the discrete point distribution diagram is obtained; a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region is obtained; and a test result of the wafer under test is obtained based on the correlation.

公开(公告)号：US12218220B2

公开(公告)日：2025-02-04

申请号：US17661359

申请日：2022-04-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Shuai Guo ,  Mingguang Zuo ,  Shijie Bai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.