公开(公告)号：US09490264B2

公开(公告)日：2016-11-08

申请号：US12984466

申请日：2011-01-04

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L27/12 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L29/732 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10873 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/78639

摘要： The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.

摘要翻译： 本发明涉及一种在绝缘体上半导体衬底上制造的半导体器件，其包括通过掩埋绝缘层与基底衬底分离的半导体材料的薄层，该器件包括薄层中的第一导电区域，第二导电层 区域和通过绝缘层将第一区域连接到第二区域的接触。 本发明还涉及制造这种半导体器件的方法。

公开(公告)号：US09159400B2

公开(公告)日：2015-10-13

申请号：US13422697

申请日：2012-03-16

申请人： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

发明人： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C11/4097

摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

摘要翻译： 具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。 每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。 这导致互连空间与位线平行。 此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

公开(公告)号：US08654602B2

公开(公告)日：2014-02-18

申请号：US13495632

申请日：2012-06-13

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

公开(公告)号：US08508289B2

公开(公告)日：2013-08-13

申请号：US13013580

申请日：2011-01-25

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

摘要翻译： 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区， ，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。 本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。 这种电路结构还包括连接背栅极控制区域的后栅极线。 本发明还提供了操作和设计这种半导体器件结构的方法。

公开(公告)号：US20110242926A1

公开(公告)日：2011-10-06

申请号：US12793553

申请日：2010-06-03

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： G11C8/08 ,  G05F1/10

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

公开(公告)号：US07919393B2

公开(公告)日：2011-04-05

申请号：US12769299

申请日：2010-04-28

申请人： Bruno Ghyselen ,  Carlos Mazure ,  Emmanuel Arene

发明人： Bruno Ghyselen ,  Carlos Mazure ,  Emmanuel Arene

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76259 ,  H01L21/324 ,  H01L21/76254 ,  H01L2221/68363

摘要： A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.

摘要翻译： 一种用于形成在衬底上包括松弛或假松弛层的结构的方法。 该方法包括在施主衬底上生长半导体材料的弹性应力层的步骤; 在应力层上形成粘性材料的玻璃状层; 去除供体衬底的一部分以形成包括玻璃层，应力层和供体衬底材料的表面层的结构; 图案化应力层; 并且在至少玻璃质层的粘度温度的温度下对结构进行热处理，以使应力层松弛以形成结构的松弛或假松弛层。

公开(公告)号：US07736988B2

公开(公告)日：2010-06-15

申请号：US11345495

申请日：2006-02-02

申请人： Bruno Ghyselen ,  Carlos Mazure ,  Emmanuel Arene

发明人： Bruno Ghyselen ,  Carlos Mazure ,  Emmanuel Arene

IPC分类号： H01L21/76 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76259 ,  H01L21/324 ,  H01L21/76254 ,  H01L2221/68363

摘要： A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.

摘要翻译： 描述了在衬底上形成松弛或假松弛有用层的方法。 该方法包括在施主衬底上生长应变半导体层，通过在某一粘度温度下变得粘稠的材料的玻璃质层将接收器衬底接合到应变半导体层以形成第一结构。 该方法还包括从第一结构分离施主衬底以形成包括接受衬底，玻璃体层和应变层的第二结构，然后在足够的温度和时间对第二结构进行热处理以使应变中的应变松弛 并且在接收器基板上形成松弛或假松弛的有用层。

公开(公告)号：US07572714B2

公开(公告)日：2009-08-11

申请号：US11221045

申请日：2005-09-06

申请人： Cécile Aulnette ,  Ian Cayrefourcq ,  Carlos Mazure

发明人： Cécile Aulnette ,  Ian Cayrefourcq ,  Carlos Mazure

IPC分类号： H01L21/30

CPC分类号： H01L21/76254

摘要： The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer. This method includes forming a step of defined height around the periphery of the wafer, with the step having a mean thickness that is less than that of the wafer; and selectively implanting atomic species through a face of the wafer but not through the step to form an implanted zone at a defined implant depth with the film being defined between the face of the wafer and the implanted zone. The implantation of atomic species into the step can be prevented by forming a protective layer at least over the step or by masking the step. The invention also relates to a wafer obtainable by the method.

摘要翻译： 本发明涉及一种从初始晶片开始制造用于电子学，光学或光电子学中的薄膜的方法，其包括通过晶片的一个表面注入原子物质的步骤。 该方法包括：形成围绕晶片周边的限定高度的台阶，其平均厚度小于晶片的平均厚度; 并且通过晶片的表面选择性地注入原子物质，但不通过该步骤，以在限定的注入深度处形成植入区域，其中膜被限定在晶片的表面和植入区域之间。 可以通过至少在该步骤上形成保护层或通过掩蔽该步骤来防止将原子物质注入到该步骤中。 本发明还涉及可通过该方法获得的晶片。

公开(公告)号：US07510949B2

公开(公告)日：2009-03-31

申请号：US11106135

申请日：2005-04-13

申请人： Carlos Mazure ,  Bruno Ghyselen

发明人： Carlos Mazure ,  Bruno Ghyselen

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L29/1054 ,  H01L21/76254 ,  H01L21/76259

摘要： Methods for producing a multilayer semiconductor structure are described. In an embodiment, the method includes providing a support substrate made of a first semiconductor material having a first lattice parameter, and depositing a layer of a second semiconductor material having a second lattice parameter, substantially different than the first, onto the support substrate to form an intermediate structure having an interface therebetween, the depositing being conducted such that most of the defects are confined to an adaptation layer located in a region adjacent to the interface. The method also includes creating a zone of weakness in the intermediate structure, bonding the second semiconductor material layer to a target substrate, detaching the support substrate at the zone to obtain a multilayer semiconductor structure having an exposed surface where detached, and fully removing the adaptation layer to obtain a relaxed thin layer of the second semiconductor material having a high quality surface.

摘要翻译： 对多层半导体结构体的制造方法进行说明。 在一个实施例中，该方法包括提供由具有第一晶格参数的第一半导体材料制成的支撑衬底，以及将具有与第一晶格参数基本上不同于第一晶格参数的第二半导体材料层沉积到支撑衬底上以形成 其间具有界面的中间结构，所述沉积被导通，使得大部分缺陷被限制在位于与界面相邻的区域中的适配层。 该方法还包括在中间结构中产生弱点区域，将第二半导体材料层粘合到目标基板上，在该区域分离支撑基板，以获得具有分离的暴露表面的多层半导体结构，并且完全去除适应 以获得具有高质量表面的第二半导体材料的松弛薄层。

公开(公告)号：US20080014712A1

公开(公告)日：2008-01-17

申请号：US11624070

申请日：2007-01-17

申请人： Konstantin Bourdelle ,  Carlos Mazure ,  Olivier Rayssac ,  Pierre Rayssac ,  Gisele Rayssac

发明人： Konstantin Bourdelle ,  Carlos Mazure ,  Olivier Rayssac ,  Pierre Rayssac ,  Gisele Rayssac

IPC分类号： H01L21/30

CPC分类号： H01L21/187

摘要： The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.

摘要翻译： 本发明提供了直接接合基底的方法，其中至少一个包括在其前表面或其附近延伸的半导体材料层。 所提供的方法包括，在接合之前，使包含半导体材料的至少一个衬底的结合面在所选择的温度和选定的气体气氛中进行选择的热处理。 键合的衬底可用于电子，光学或光电子应用。