公开(公告)号：US20110117723A1

公开(公告)日：2011-05-19

申请号：US13014771

申请日：2011-01-27

Applicant: Robert Seidel ,  Carsten Peters ,  Frank Feustel

Inventor： Robert Seidel ,  Carsten Peters ,  Frank Feustel

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/28

CPC classification number: B81B7/0006 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/28114 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76817 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2221/1021

Abstract: By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.

Abstract translation: 通过基于压印技术形成金属化结构，其中可以通常形成通孔和沟槽，由于根据常规工艺技术所要求的至少一个进一步对准过程，可以实现工艺复杂性的显着降低。 此外，可以通过提供适当设计的压印模具来提高压印光刻的灵活性和效率，以便提供表现出增加的填充能力的通孔开口和沟槽，从而也提高了最终获得的金属化结构在可靠性，抗性 电迁移等。

公开(公告)号：US07910496B2

公开(公告)日：2011-03-22

申请号：US12020234

申请日：2008-01-25

Applicant: Frank Feustel ,  Kai Frohberg ,  Carsten Peters

Inventor： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

IPC: H01L21/76

CPC classification number: H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

Abstract: By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

Abstract translation: 通过去除通过SACVD沉积的层间电介质材料的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可能降低该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间电介质材料之前形成诸如二氧化硅的缓冲材料，从而当在具有不同高度固有的电介质层上沉积层间电介质材料时在沉积过程中产生增强的均匀性 压力水平。 因此，可以提高层间绝缘材料的可靠性，同时保持由SACVD沉积提供的优点。

公开(公告)号：US07879709B2

公开(公告)日：2011-02-01

申请号：US12060563

申请日：2008-04-01

Applicant: Frank Feustel ,  Tobias Letz ,  Carsten Peters

Inventor： Frank Feustel ,  Tobias Letz ,  Carsten Peters

IPC: H01L21/00

CPC classification number: H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material.

Abstract translation: 半导体结构包括半导体衬底。 在半导体衬底上形成电绝缘材料层。 在电绝缘材料层中形成导电特征。 在导电特征和电绝缘材料层之间形成第一层半导体材料。

公开(公告)号：US07785956B2

公开(公告)日：2010-08-31

申请号：US12168443

申请日：2008-07-07

Applicant: Ralf Richter ,  Robert Seidel ,  Carsten Peters

Inventor： Ralf Richter ,  Robert Seidel ,  Carsten Peters

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

Abstract translation: 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

公开(公告)号：US07608501B2

公开(公告)日：2009-10-27

申请号：US11425942

申请日：2006-06-22

Applicant: Kai Frohberg ,  Carsten Peters ,  Matthias Schaller ,  Heike Salz

Inventor： Kai Frohberg ,  Carsten Peters ,  Matthias Schaller ,  Heike Salz

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843 ,  Y10S438/97

Abstract: By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device having different types of transistors may be provided, in which a high degree of metal silicide integrity as well as a highly efficient stress transfer mechanism is achieved.

Abstract translation: 通过在形成第一接触蚀刻停止层之前部分地去除蚀刻停止层，可以以用于通过接触蚀刻停止层产生应变的积分方案来提供优异的应力传递机制。 因此，可以提供具有不同类型的晶体管的半导体器件，其中实现高度的金属硅化物完整性以及高效应力传递机制。

公开(公告)号：US20090085145A1

公开(公告)日：2009-04-02

申请号：US12060563

申请日：2008-04-01

Applicant: Frank Feustel ,  Tobias Letz ,  Carsten Peters

Inventor： Frank Feustel ,  Tobias Letz ,  Carsten Peters

IPC: H01L21/768 ,  H01L29/47 ,  H01L21/20

CPC classification number: H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material.

Abstract translation: 半导体结构包括半导体衬底。 在半导体衬底上形成电绝缘材料层。 在电绝缘材料层中形成导电特征。 在导电特征和电绝缘材料层之间形成第一层半导体材料。

公开(公告)号：US20090061645A1

公开(公告)日：2009-03-05

申请号：US12044049

申请日：2008-03-07

Applicant: Ralf Richter ,  Carsten Peters ,  Juergen Boemmels

Inventor： Ralf Richter ,  Carsten Peters ,  Juergen Boemmels

IPC: H01L21/31

CPC classification number: H01L21/324 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: By appropriately treating an interlayer dielectric material above P-channel transistors, the compressive stress may be significantly enhanced, which may be accomplished by expanding the interlayer dielectric material, for instance, by providing a certain amount of oxidizable species and performing an oxidation process.

Abstract translation: 通过适当地处理P沟道型晶体管以上的层间电介质材料，可以显着地提高压缩应力，这可以通过例如提供一定量的可氧化物质并进行氧化工艺来扩展层间电介质材料来实现。

公开(公告)号：US20090001526A1

公开(公告)日：2009-01-01

申请号：US12020234

申请日：2008-01-25

Applicant: Frank Feustel ,  Kai Frohberg ,  Carsten Peters

Inventor： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

Abstract: By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

Abstract translation: 通过去除通过SACVD沉积的层间电介质材料的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可能降低该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间电介质材料之前形成诸如二氧化硅的缓冲材料，从而当在具有不同高度固有的电介质层上沉积层间电介质材料时在沉积过程中产生增强的均匀性 压力水平。 因此，可以提高层间绝缘材料的可靠性，同时保持由SACVD沉积提供的优点。

公开(公告)号：US20080265419A1

公开(公告)日：2008-10-30

申请号：US11944039

申请日：2007-11-21

Applicant: Kai Frohberg ,  Frank FEUSTEL ,  Carsten PETERS

Inventor： Kai Frohberg ,  Frank FEUSTEL ,  Carsten PETERS

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. A first glue layer and a second glue layer are formed over the recess. The first glue layer comprises titanium and the second glue layer comprises tungsten nitride. The recess is filled with a material comprising tungsten.

Abstract translation: 形成半导体结构的方法包括提供包括电介质材料层的半导体衬底。 在介电材料层中设置凹部。 在凹部上形成第一胶层和第二胶层。 第一胶层包括钛，第二胶层包括氮化钨。 凹部填充有包含钨的材料。

公开(公告)号：US20080132057A1

公开(公告)日：2008-06-05

申请号：US11757022

申请日：2007-06-01

Applicant: Frank Feustel ,  Carsten Peters ,  Thomas Foltyn

Inventor： Frank Feustel ,  Carsten Peters ,  Thomas Foltyn

IPC: H01L21/4763

CPC classification number: H01L21/76844

Abstract: By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom of a via in advanced metallization structures of highly scaled semiconductor devices.

Abstract translation: 通过在自限制沉积工艺之前或期间提供表面改性方法，可以选择性地改变本身高共形沉积行为，以便在比表面积获得可靠的覆盖，同时显着地减少或抑制不想要的表面积 ，例如高分辨率半导体器件的先进金属化结构中的通孔的底部。