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1.发明授权公开(公告)号：US08492079B2
公开(公告)日：2013-07-23
申请号：US12430919
申请日：2009-04-28
申请人： Chia-Chen Chen , Wu-Song Huang , Wai-Kin Li , Chandrasekhar Sarma
发明人： Chia-Chen Chen , Wu-Song Huang , Wai-Kin Li , Chandrasekhar Sarma
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F1/70 , G03F7/095 , G03F7/203 , Y10T428/24802
摘要： A second photoresist having a second photosensitivity is formed on a substrate. A first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on the second photoresist. Preferably, the first photoresist is a gray resist that becomes transparent upon exposure. At least one portion of the first photoresist is lithographically exposed employing a first reticle having a first pattern to form at least one transparent lithographically exposed resist portion, while the second photoresist remains intact. The second photoresist is lithographically exposed employing a second reticle including a second pattern to form a plurality of lithographically exposed shapes in the second photoresist. The plurality of lithographically exposed shapes have a composite pattern which is the derived from the second pattern by limiting the second pattern only within the area of the at least one transparent lithographically exposed resist pattern.
摘要翻译： 在基板上形成具有第二光敏性的第二光致抗蚀剂。 在第二光致抗蚀剂上形成具有大于第二光敏性的第一光敏性的第一光致抗蚀剂。 优选地，第一光致抗蚀剂是在曝光时变得透明的灰色抗蚀剂。 使用具有第一图案的第一掩模版将第一光致抗蚀剂的至少一部分光刻曝光以形成至少一个透明的光刻曝光的抗蚀剂部分，而第二光致抗蚀剂保持完整。 使用包括第二图案的第二掩模版将第二光致抗蚀剂光刻曝光，以在第二光致抗蚀剂中形成多个光刻曝光的形状。 多个光刻曝光的形状具有通过仅在至少一个透明光刻曝光的抗蚀剂图案的区域内限制第二图案而从第二图案导出的复合图案。
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2.发明授权公开(公告)号：US08377800B2
公开(公告)日：2013-02-19
申请号：US13453848
申请日：2012-04-23
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.
摘要翻译： 用偏光光刻技术集成电路制造的标记和方法。 优选实施例包括由第一部件类型构成的第一多个元件，其中第一元件类型具有第一偏振，第二元件类型具有第二元件类型，其中第二元件类型具有第二偏振，其中 第一极化和第二极化是正交的，其中相邻元件是不同的组件类型。 对准标记可以用于基于强度或基于衍射的对准过程。
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公开(公告)号：US08359562B2
公开(公告)日：2013-01-22
申请号：US13004562
申请日：2011-01-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , B33Y80/00 , G03F1/70
摘要： In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display.
摘要翻译： 在一个实施例中，制造半导体器件的方法包括使用处理器来使用目标结构的布局掩模来生成用于第一处理条件的第一三维（3-D）抗蚀剂轮廓。 该方法还包括使用处理器使用布局掩模来生成用于第二处理条件的第二3-D抗蚀剂轮廓。 第一处理条件包括多个处理变量，并且第二处理条件包括多于第一处理条件的多个处理变量的不同值。 该方法包括通过组合第一3-D抗蚀剂轮廓和第二3-D抗蚀剂轮廓来产生3-D过程变量（PV）带轮廓，并在显示器上显示3-D PV带轮廓的3-D图像 。
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公开(公告)号：US20120179282A1
公开(公告)日：2012-07-12
申请号：US13004562
申请日：2011-01-11
CPC分类号： G06F17/5068 , B33Y80/00 , G03F1/70
摘要： In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display.
摘要翻译： 在一个实施例中，制造半导体器件的方法包括使用处理器来使用目标结构的布局掩模来生成用于第一处理条件的第一三维（3-D）抗蚀剂轮廓。 该方法还包括使用处理器使用布局掩模来生成用于第二处理条件的第二3-D抗蚀剂轮廓。 第一处理条件包括多个处理变量，并且第二处理条件包括多于第一处理条件的多个处理变量的不同值。 该方法包括通过组合第一3-D抗蚀剂轮廓与第二3-D抗蚀剂轮廓并在显示器上显示3-D PV带轮廓的3-D图像来产生3-D过程变量（PV） 。
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5.发明授权公开(公告)号：US08183129B2
公开(公告)日：2012-05-22
申请号：US12694105
申请日：2010-01-26
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.
摘要翻译： 用偏光光刻技术集成电路制造的标记和方法。 优选实施例包括由第一部件类型构成的第一多个元件，其中第一元件类型具有第一偏振，第二元件类型具有第二元件类型，其中第二元件类型具有第二偏振，其中 第一极化和第二极化是正交的，其中相邻元件是不同的组件类型。 对准标记可以用于基于强度或基于衍射的对准过程。
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6.发明申请Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit 审中-公开集成电路中介质上可调谐的多晶硅公开(公告)号：US20110089501A1
公开(公告)日：2011-04-21
申请号：US12978730
申请日：2010-12-27
CPC分类号： H01L29/7843 , H01L21/02145 , H01L21/02178 , H01L21/285 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L29/04 , H01L29/0653 , H01L29/16 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78 , H01L29/7845 , H01L29/7846
摘要： A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed.
摘要翻译： 公开了一种形成集成电路器件的方法。 形成与电介质材料直接接触的多晶硅层，使得介电材料在形成多晶硅层时在多晶硅层中引起应力。 然后完成包括包括多晶硅的栅极的MOS晶体管。
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公开(公告)号：US20100120177A1
公开(公告)日：2010-05-13
申请号：US12691218
申请日：2010-01-21
IPC分类号： H01L21/66 , H01L21/3065 , H01L21/308 , H01L21/306
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译： 公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。 还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于 物理特性，并根据蚀刻控制参数刻蚀该层。
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公开(公告)号：US20080119048A1
公开(公告)日：2008-05-22
申请号：US11602886
申请日：2006-11-21
IPC分类号： H01L21/302
CPC分类号： G03F1/50 , G02B5/3083 , Y10T428/24479
摘要： Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the second pattern comprising patterns for features oriented differently than patterns for features of the first pattern. The method includes affecting a polarization rotation of light differently in the first region than in the second region of the substrate.
摘要翻译： 公开了平版印刷掩模及其制造方法。 优选实施例包括制造光刻掩模的方法。 所述方法包括提供衬底，在所述衬底的第一区域中形成第一图案，以及在所述衬底的第二区域中形成第二图案，所述第二图案包括不同于第一图案特征的图案的图案。 该方法包括在第一区域中比在衬底的第二区域中影响光的偏振旋转。
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公开(公告)号：US20070239305A1
公开(公告)日：2007-10-11
申请号：US11390696
申请日：2006-03-28
IPC分类号： G06F19/00
摘要： Process control systems and methods for semiconductor device manufacturing are disclosed. A plurality of feedback and feed-forward loops are used to accurately control the critical dimension (CD) of features formed on material layers of semiconductor devices. Semiconductor devices with features having substantially the same dimension for each die across the surface of a wafer may be fabricated using the novel process control systems and methods described herein.
摘要翻译： 公开了用于半导体器件制造的工艺控制系统和方法。 使用多个反馈和前馈环来精确地控制在半导体器件的材料层上形成的特征的临界尺寸（CD）。 可以使用本文所述的新颖的工艺控制系统和方法来制造具有对于晶片表面上的每个管芯具有基本相同尺寸的特征的半导体器件。
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公开(公告)号：US20110250530A1
公开(公告)日：2011-10-13
申请号：US13164139
申请日：2011-06-20
CPC分类号： H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.
摘要翻译： 公开了半导体器件及其制造方法。 多个特征形成在工件上，多个特征位于工件的第一区域和第二区域中。 第一区域中的特征具有第一横向尺寸，并且第二区域中的特征具有第二横向尺寸，其中第二横向尺寸大于第一横向尺寸。 第一区域被掩蔽，并且第二区域中的特征的第二横向尺寸减小。
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