公开(公告)号：US07825713B2

公开(公告)日：2010-11-02

申请号：US12286765

申请日：2008-10-02

申请人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

发明人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

IPC分类号： H03H11/26

CPC分类号： G06F1/14

摘要： An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.

摘要翻译： 绝对时间延迟产生装置包括PVT（过程电压 - 温度）检测装置和延迟定时发生器。 PVT检测装置至少包括延迟模块和信号相位/频率控制模块。 延迟模块包括控制单元和参考单元。 控制单元与PVT的延迟属性的灵敏度不同于参考单元。 延迟模块比较原点信号分别通过控制单元和参考单元产生的相位或频率差，并产生延迟模块的延迟参数。 信号相位/频率控制模块接收并比较延迟参数以确定绝对时间延迟产生装置的环境PVT条件，以便控制和校正延迟定时发生器从而产生精确的绝对时间延迟。 在各种PVT影响下，绝对时间延迟产生装置能够产生精确的绝对时间信号。

公开(公告)号：US20130038369A1

公开(公告)日：2013-02-14

申请号：US13352350

申请日：2012-01-18

申请人： Chen-Yi LEE ,  Chien-Ying YU ,  Chia-Jung YU

发明人： Chen-Yi LEE ,  Chien-Ying YU ,  Chia-Jung YU

IPC分类号： H03K5/06

CPC分类号： H03L7/0997

摘要： A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

摘要翻译： 延迟单元包括第一反相晶体管对，第二反相晶体管对和多个延迟单元。 第一反相晶体管对用于接收输入信号。 第二反相晶体管对与第一反相晶体管对电交叉耦合并由第一反相晶体管对交叉控制。 延迟单元在第一反相晶体管对之间和第二反向晶体管对之间级联，从而依次提供多个信号传播延迟，其中输入信号被第一反相晶体管对延迟预定时间，第二 反相晶体管对和延迟单元，从而产生与预定时间对应的输出信号。 提供了包括上述延迟单元的数字控制振荡器。

公开(公告)号：US08466729B2

公开(公告)日：2013-06-18

申请号：US13352350

申请日：2012-01-18

申请人： Chen-Yi Lee ,  Chien-Ying Yu ,  Chia-Jung Yu

发明人： Chen-Yi Lee ,  Chien-Ying Yu ,  Chia-Jung Yu

IPC分类号： H03H11/26

CPC分类号： H03L7/0997

摘要： A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

摘要翻译： 延迟单元包括第一反相晶体管对，第二反相晶体管对和多个延迟单元。 第一反相晶体管对用于接收输入信号。 第二反相晶体管对与第一反相晶体管对电交叉耦合并由第一反相晶体管对交叉控制。 延迟单元在第一反相晶体管对之间和第二反向晶体管对之间级联，从而依次提供多个信号传播延迟，其中输入信号被第一反相晶体管对延迟预定时间，第二 反相晶体管对和延迟单元，从而产生与预定时间对应的输出信号。 提供了包括上述延迟单元的数字控制振荡器。

公开(公告)号：US20100013536A1

公开(公告)日：2010-01-21

申请号：US12286765

申请日：2008-10-02

申请人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

发明人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

IPC分类号： H03H11/26

CPC分类号： G06F1/14

摘要： An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.