公开(公告)号：US09489989B2

公开(公告)日：2016-11-08

申请号：US12820712

申请日：2010-06-22

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: G11C11/22 ,  G11C11/24 ,  G11C7/06 ,  G11C5/14 ,  G11C8/00

CPC classification number: G11C11/4074 ,  G11C5/147

Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

Abstract translation: 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

公开(公告)号：US20160087817A1

公开(公告)日：2016-03-24

申请号：US14492237

申请日：2014-09-22

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

IPC: H04L25/03 ,  H04L25/06 ,  H04L25/08

CPC classification number: H04L25/03057 ,  H04L25/06 ,  H04L25/08

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract translation: 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

公开(公告)号：US08854104B2

公开(公告)日：2014-10-07

申请号：US13793681

申请日：2013-03-11

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang

IPC: H03L5/00

CPC classification number: H03L5/00 ,  H03K3/356182 ,  H03K17/102 ,  H03K19/018521

Abstract: A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.

Abstract translation: 电路包括第一电容性装置和第一锁存器。 第一电容性装置包括被配置为接收第一输入信号的第一端和与第一锁存器耦合的第二端。 第一锁存器包括第一类型的第一晶体管和第二晶体管。 第一晶体管的第一端子和第二晶体管的第一端子都被配置为接收第一电压值。 第一晶体管的第二端与第二晶体管的第三端耦合。 第一晶体管的第三端子与第二晶体管的第二端子和电容器件的第二端耦合，并且被配置为提供用于第一锁存器的输出电压。

公开(公告)号：US08766613B2

公开(公告)日：2014-07-01

申请号：US13744037

申请日：2013-01-17

Applicant: Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

Inventor： Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

Abstract translation: 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

公开(公告)号：US20140037035A1

公开(公告)日：2014-02-06

申请号：US13564758

申请日：2012-08-02

Applicant: Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: H03D3/24

CPC classification number: H03K5/135 ,  H03H11/20 ,  H03K2005/00052 ,  H04L7/0029

Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

Abstract translation: 用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。 输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。 差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。 输出时钟是线性的，只要两个输入时钟的转换重叠即可。 每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。

公开(公告)号：US08629704B2

公开(公告)日：2014-01-14

申请号：US12717705

申请日：2010-03-04

Applicant: Tien Chun Yang ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu

Inventor： Tien Chun Yang ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu

IPC: H03L5/00

CPC classification number: H03K19/017509 ,  H03K19/018521 ,  H05K13/00 ,  Y10T29/49117

Abstract: A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor.

Abstract translation: 电平移位器包括能够接收输入电压信号的输入端。 输入电压信号包括从第一电压状态到第二电压状态的第一状态转变。 输出端可以输出具有从第三电压状态到对应于输入电压信号的第一状态转换的第二电压状态的第二状态转换的输出电压信号。 驱动级连接在输入端和输出端之间。 驱动器级包括第一晶体管和第二晶体管。 基本上从与第一电压状态和第二电压状态的电压电平的平均值相对应的时间基本上立即，第二电压状态基本上没有被施加到第一晶体管的栅极，以便基本上关闭第一晶体管 。

公开(公告)号：US08625240B2

公开(公告)日：2014-01-07

申请号：US13293853

申请日：2011-11-10

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H02H3/22

CPC classification number: H02H9/04 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H03F2200/294 ,  H03F2203/45638 ,  H03G1/0023 ,  H03K3/35613 ,  H03K19/018514 ,  H01L2924/00

Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.

Abstract translation: 输入/输出（I / O）电路包括与I / O电路的输出节点电耦合的静电放电（ESD）保护电路。 至少一个电感器和至少一个负载以串联方式电耦合，并且在I / O电路的输出节点和电力线之间。 电路与所述至少一个电感器和所述至少一个负载之间的节点电耦合。 电路可操作以在信号转换期间增加流过至少一个电感器的电流。

公开(公告)号：US08588358B2

公开(公告)日：2013-11-19

申请号：US13045788

申请日：2011-03-11

Applicant: Chan-Hong Chern ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/113 ,  H04L7/0337

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

Abstract translation: 时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。 延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。 电荷泵配置为控制LCVCO。 相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

公开(公告)号：US20130190482A1

公开(公告)日：2013-07-25

申请号：US13560593

申请日：2012-07-27

Applicant: Hua-Wen Fu ,  Kuo-Shun Shih ,  Chih-Chang Lin ,  Yu-Chi Yang

Inventor： Hua-Wen Fu ,  Kuo-Shun Shih ,  Chih-Chang Lin ,  Yu-Chi Yang

IPC: C07K1/22

CPC classification number: C07K14/205

Abstract: Helicobacter pylori is closely associated with chronic gastritis, peptic ulcer disease, and gastric adenocarcinoma. Helicobacter pylori neutrophil-activating protein (HP-NAP), a virulence factor of Helicobacter pylori, plays an important role in pathogenesis of Helicobacter pylori infection. Since HP-NAP has been proposed as a candidate vaccine against Helicobacter pylori infection, an efficient way to obtain pure HP-NAP needs to be developed. In the present invention, recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli was purified through a single step of DEAE Sephadex ion-exchange chromatography with high purity. Also, purified recombinant HP-NAP was able to stimulate neutrophils to produce reactive oxygen species. Thus, recombinant HP-NAP obtained from our Bacillus subtilis expression system and Escherichia coli expression system is functionally active. Furthermore, this one-step negative purification method should provide an efficient way to purify recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli for basic studies, vaccine development, or drug design.

Abstract translation: 幽门螺杆菌与慢性胃炎，消化性溃疡病和胃腺癌密切相关。 幽门螺杆菌嗜中性粒细胞激活蛋白（HP-NAP）是幽门螺杆菌的毒力因子，在幽门螺杆菌感染的发病机制中起重要作用。 由于HP-NAP已被提出作为针对幽门螺杆菌感染的候选疫苗，因此需要开发获得纯HP-NAP的有效途径。 在本发明中，通过单纯DEAE Sephadex离子交换层析纯化纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP。 此外，纯化的重组HP-NAP能够刺激嗜中性粒细胞产生活性氧。 因此，从我们的枯草芽孢杆菌表达系统和大肠杆菌表达系统获得的重组HP-NAP在功能上是活性的。 此外，该一步负纯化方法应提供一种有效的方法来纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP用于基础研究，疫苗开发或药物设计。

公开(公告)号：US08493124B2

公开(公告)日：2013-07-23

申请号：US12843479

申请日：2010-07-26

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract translation: 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。