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601 条记录 (耗时 0.023 秒)

    Method to fabricate copper wiring structures and structures formed thereby
    2.
    发明授权
    Method to fabricate copper wiring structures and structures formed thereby 有权
    制造铜布线结构和由此形成的结构的方法

    公开(公告)号：US09048296B2

    公开(公告)日：2015-06-02

    申请号：US13025322

    申请日：2011-02-11

    申请人： Fenton Read McFeely ,  Chih-Chao Yang

    发明人： Fenton Read McFeely ,  Chih-Chao Yang

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

    摘要翻译： 提供了高纯铜（Cu）填充线和通孔的技术形成。 在一个方面，提供了一种制造填充有高纯度铜的管线和通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 通过溅射工艺在Ru层上沉积Cu层。 进行回流退火以消除管线和通孔中的空隙。

    Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices
    5.
    发明授权
    Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices 失效
    减少半导体器件中电迁移破裂和挤出效应的结构和方法

    公开(公告)号：US08716101B2

    公开(公告)日：2014-05-06

    申请号：US13530999

    申请日：2012-06-22

    申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L21/76

    CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

    摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

    Structure and process for conductive contact integration
    6.
    发明授权
    Structure and process for conductive contact integration 有权
    导电触点集成的结构和工艺

    公开(公告)号：US08679970B2

    公开(公告)日：2014-03-25

    申请号：US12124698

    申请日：2008-05-21

    申请人： Chih-Chao Yang ,  Lynne M. Gignac

    发明人： Chih-Chao Yang ,  Lynne M. Gignac

    IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L21/768

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76864 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.

    摘要翻译： 提供了一种半导体结构，其包括消除了键孔形成的高可靠性高纵横比接触结构。 在本发明中通过在存在于电介质材料中的高纵横比接触开口内提供致密的含贵金属衬里来消除键孔缝形成。 致密化的含贵金属的衬里位于扩散阻挡层的顶部，并且这两个元件将本发明接触结构的导电材料与下面的半导体结构的导电材料分开。 通过沉积具有第一电阻率的含贵金属的材料形成本发明的含致密化的含贵金属的衬里，并使沉积的含贵金属的材料经受降低电阻率的致密化处理（热或等离子体） 的沉积的含贵金属材料的电阻率较低。

    Interconnect structures and methods for back end of the line integration
    8.
    发明授权
    Interconnect structures and methods for back end of the line integration 失效
    用于线路集成后端的互连结构和方法

    公开(公告)号：US08637400B2

    公开(公告)日：2014-01-28

    申请号：US13164940

    申请日：2011-06-21

    申请人： David V. Horak ,  Charles W. Koburger ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： David V. Horak ,  Charles W. Koburger ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/52

    CPC分类号： G06F17/5077 ,  H01L21/76834 ,  H01L21/76885

    摘要： A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

    摘要翻译： 形成半导体结构的方法包括形成牺牲导电材料层。 该方法还包括在牺牲导电材料层中形成沟槽。 该方法还包括在沟槽中形成导电特征。 该方法还包括去除对导电特征有选择性的牺牲导电材料层。 该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层中。

    Tungsten metallization: structure and fabrication of same
    9.
    发明授权
    Tungsten metallization: structure and fabrication of same 失效
    钨金属化：其结构和制造相同

    公开(公告)号：US08564132B2

    公开(公告)日：2013-10-22

    申请号：US13211722

    申请日：2011-08-17

    申请人： Chih-Chao Yang ,  Daniel C. Edelstein

    发明人： Chih-Chao Yang ,  Daniel C. Edelstein

    IPC分类号： H01L23/482

    CPC分类号： H01L21/76838 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76895

    摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

    摘要翻译： 提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。 这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。 在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。 然后形成与第一互连图案相邻但不连接的第二布线图案。 由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。