公开(公告)号：US09245794B2

公开(公告)日：2016-01-26

申请号：US13614492

申请日：2012-09-13

Applicant: Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

Inventor： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

IPC: H05K1/09 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

Abstract translation: 提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。 本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。 在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

公开(公告)号：US09048296B2

公开(公告)日：2015-06-02

申请号：US13025322

申请日：2011-02-11

Applicant: Fenton Read McFeely ,  Chih-Chao Yang

Inventor： Fenton Read McFeely ,  Chih-Chao Yang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Abstract translation: 提供了高纯铜（Cu）填充线和通孔的技术形成。 在一个方面，提供了一种制造填充有高纯度铜的管线和通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 通过溅射工艺在Ru层上沉积Cu层。 进行回流退火以消除管线和通孔中的空隙。

公开(公告)号：US08907458B2

公开(公告)日：2014-12-09

申请号：US13407933

申请日：2012-02-29

Applicant: Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

Inventor： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

公开(公告)号：US08772156B2

公开(公告)日：2014-07-08

申请号：US12118161

申请日：2008-05-09

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76849 ,  H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Abstract translation: 提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。 该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。 第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

公开(公告)号：US08716101B2

公开(公告)日：2014-05-06

申请号：US13530999

申请日：2012-06-22

Applicant: Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

Inventor： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC: H01L21/76

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

Abstract translation: 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

公开(公告)号：US08679970B2

公开(公告)日：2014-03-25

申请号：US12124698

申请日：2008-05-21

Applicant: Chih-Chao Yang ,  Lynne M. Gignac

Inventor： Chih-Chao Yang ,  Lynne M. Gignac

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76864 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.

Abstract translation: 提供了一种半导体结构，其包括消除了键孔形成的高可靠性高纵横比接触结构。 在本发明中通过在存在于电介质材料中的高纵横比接触开口内提供致密的含贵金属衬里来消除键孔缝形成。 致密化的含贵金属的衬里位于扩散阻挡层的顶部，并且这两个元件将本发明接触结构的导电材料与下面的半导体结构的导电材料分开。 通过沉积具有第一电阻率的含贵金属的材料形成本发明的含致密化的含贵金属的衬里，并使沉积的含贵金属的材料经受降低电阻率的致密化处理（热或等离子体） 的沉积的含贵金属材料的电阻率较低。

公开(公告)号：US08637957B1

公开(公告)日：2014-01-28

申请号：US13552293

申请日：2012-07-18

Applicant: Chih-Chao Yang ,  Stephen M. Gates

Inventor： Chih-Chao Yang ,  Stephen M. Gates

IPC: H01L29/00

CPC classification number: H01L23/5252 ,  G11C17/165 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53247 ,  H01L23/5329 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.

Abstract translation: 提供一种抗熔丝结构，其中抗熔丝材料衬垫嵌入设置在互连电介质材料内的一个开口内。 反熔丝材料衬垫位于第一导电金属和第二导电金属之间，第一导电金属和第二导电金属也存在于开口内。 扩散阻挡衬里将第一导电金属与互连电介质材料的任何部分分开。 反熔丝结构横向邻近形成在与反熔丝结构相同的互连电介质材料内的互连结构。

公开(公告)号：US08637400B2

公开(公告)日：2014-01-28

申请号：US13164940

申请日：2011-06-21

Applicant: David V. Horak ,  Charles W. Koburger ,  Shom Ponoth ,  Chih-Chao Yang

Inventor： David V. Horak ,  Charles W. Koburger ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/52

CPC classification number: G06F17/5077 ,  H01L21/76834 ,  H01L21/76885

Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

Abstract translation: 形成半导体结构的方法包括形成牺牲导电材料层。 该方法还包括在牺牲导电材料层中形成沟槽。 该方法还包括在沟槽中形成导电特征。 该方法还包括去除对导电特征有选择性的牺牲导电材料层。 该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层中。

公开(公告)号：US08564132B2

公开(公告)日：2013-10-22

申请号：US13211722

申请日：2011-08-17

Applicant: Chih-Chao Yang ,  Daniel C. Edelstein

Inventor： Chih-Chao Yang ,  Daniel C. Edelstein

IPC: H01L23/482

CPC classification number: H01L21/76838 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76895

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract translation: 提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。 这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。 在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。 然后形成与第一互连图案相邻但不连接的第二布线图案。 由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。

公开(公告)号：US08558384B2

公开(公告)日：2013-10-15

申请号：US13537879

申请日：2012-06-29

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract translation: 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。