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    Optical couplers and methods for making same
    2.
    发明授权
    Optical couplers and methods for making same 有权
    光耦合器及其制作方法

    公开(公告)号：US09014522B2

    公开(公告)日：2015-04-21

    申请号：US13996916

    申请日：2011-12-21

    申请人： Imtiaz Majid ,  Chih-Hao Wang ,  Kanishka Tankala

    发明人： Imtiaz Majid ,  Chih-Hao Wang ,  Kanishka Tankala

    IPC分类号： G02B6/26 ,  G02B6/27 ,  G02B6/28 ,  B29D11/00 ,  G02B6/02 ,  H01S3/067 ,  H01S3/07 ,  H01S3/094

    CPC分类号： G02B6/274 ,  B29D11/00711 ,  G02B6/02109 ,  G02B6/2843 ,  H01S3/06712 ,  H01S3/0675 ,  H01S3/07 ,  H01S3/094011 ,  H01S3/094019 ,  H01S3/09408

    摘要： The present invention relates generally to optical waveguides for the transmission of electromagnetic energy. The present invention relates more particularly to optical couplers for coupling optical fibers, and methods for making them. One aspect of the present invention is an optical coupler for use with a polarization-maintaining input optical fiber and a polarization-maintaining output optical fiber. The coupler includes: a tube having a wide end, a narrow end having an end face, and a taper therebetween; a polarization-maintaining feed-through optical fiber having a first end having an end face and a second end, the polarization-maintaining feed-through optical fiber being disposed within the tube from the wide end to the narrow end, at least the narrow end of the tube being fused around a first length of the polarization-maintaining feed-through optical fiber including the first end of the polarization-maintaining feed-through optical fiber to form a coupler end face comprising the end face of the tube and the end face of the first end of the polarization-maintaining feed-through optical fiber. In one aspect of the invention, the polarization-maintaining feed-through optical fiber has an outer diameter no greater than about 200 μm in the region in which the tube is fused around it. In another aspect of the invention, the polarization-maintaining feed-through optical fiber has an outer diameter at the coupler end face no greater than about 75% of the diameter of the polarization-maintaining input optical fiber.

    摘要翻译： 本发明一般涉及用于传输电磁能的光波导。 本发明更具体地涉及用于耦合光纤的光耦合器及其制造方法。 本发明的一个方面是一种用于偏振保持输入光纤和偏振保持输出光纤的光耦合器。 联接器包括：具有宽端的管，具有端面的窄端和其间的锥形; 一种偏振保持馈通光纤，其具有端面和第二端的第一端，所述偏振保持馈通光纤从宽端至窄端设置在管内，至少窄端 所述管被围绕包括所述偏振保持馈通光纤的所述第一端的所述偏振保持馈通光纤的第一长度熔合以形成包括所述管的端面和所述端面的耦合器端面 的偏振保持馈通光纤的第一端。 在本发明的一个方面，偏振保持馈通光纤在其周围熔合的区域中具有不大于约200μm的外径。 在本发明的另一方面，偏振保持馈通光纤在耦合器端面处的外径不大于偏振波保持输入光纤的直径的大约75％。

    Three-wheeled motor vehicle with high safety
    4.
    发明授权
    Three-wheeled motor vehicle with high safety 有权
    三轮汽车安全性高

    公开(公告)号：US08596660B2

    公开(公告)日：2013-12-03

    申请号：US13352356

    申请日：2012-01-18

    申请人： Mau-Pin Hsu ,  Hsin-Wei Su ,  Chih-Hao Wang

    发明人： Mau-Pin Hsu ,  Hsin-Wei Su ,  Chih-Hao Wang

    IPC分类号： B60K5/02 ,  B60K5/04

    CPC分类号： B62K5/10 ,  B62K5/025

    摘要： A three-wheeled motor vehicle includes a main body, two shafts, two wheel bases, a blocking structure fixed to the main body and a linkage module. Each shaft has first, second and third pivot points. The third pivot point between the first and second pivot points is pivoted to the main body. One wheel base is pivoted to the first pivot points. The other wheel base is pivoted to the second pivot points. The wheel bases and the shafts form a parallelogram four bar mechanism. The linkage module is coupled between the main body and the parallelogram four bar mechanism. When the main body tilts as the three-wheeled motor vehicle turning, the linkage module changes from a first state to a second state to drive the wheel bases to tilt.The linkage module in the second state leans against the blocking structure to limit the tilt range of the wheel bases.

    摘要翻译： 三轮机动车辆包括主体，两个轴，两个轮基座，固定在主体上的阻挡结构和连杆模块。 每个轴具有第一，第二和第三枢轴点。 第一和第二枢转点之间的第三枢转点枢转到主体。 一个车轮底座枢转到第一枢轴点。 另一个轮毂基座枢转到第二枢转点。 车轮底座和轴形成平行四边形四杆机构。 联动模块连接在主体和平行四边形四杆机构之间。 当主体以三轮机动车辆转弯的方式倾斜时，联动模块从第一状态变为第二状态，以驱动车轮底座倾斜。 处于第二状态的联动模块倾斜于阻挡结构以限制车轮基座的倾斜范围。

    High performance CMOS device design
    5.
    发明授权
    High performance CMOS device design 有权
    高性能CMOS器件设计

    公开(公告)号：US08507951B2

    公开(公告)日：2013-08-13

    申请号：US12330961

    申请日：2008-12-09

    申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Ching-Wei Tsai ,  Ta-Wei Wang ,  Pang-Yen Tsai

    发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Ching-Wei Tsai ,  Ta-Wei Wang ,  Pang-Yen Tsai

    IPC分类号： H01L29/66

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/66553 ,  H01L29/66636

    摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.

    摘要翻译： 半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物 以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。 缓冲层优选具有比下面的半导体衬底更大的晶格常数。 半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

    High performance CMOS devices and methods for making same
    7.
    发明授权
    High performance CMOS devices and methods for making same 有权
    高性能CMOS器件及其制作方法

    公开(公告)号：US08067280B2

    公开(公告)日：2011-11-29

    申请号：US12191868

    申请日：2008-08-14

    申请人： Chih-Hao Wang ,  Ta-Wei Wang ,  Chenming Hu

    发明人： Chih-Hao Wang ,  Ta-Wei Wang ,  Chenming Hu

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7833 ,  H01L29/105 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

    摘要： An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

    摘要翻译： 可以通过在衬底上形成栅极结构来形成具有良好短沟道效应的高性能CMOS器件的集成电路; 在衬底中形成袋状注入区域和源极/漏极延伸部分; 沿着栅极结构的侧面形成间隔物; 并且在形成间隔物时对衬底进行热退火，在超低温下进行热退火。 具有低寄生结电容的高性能CMOS器件的集成电路可以通过在衬底上形成栅极结构来形成; 在衬底中形成袋状注入区域和源极/漏极延伸部分; 沿着栅极结构的侧面形成间隔物; 执行低剂量源/排出植入物; 并执行高剂量源/漏植入物。

    Method for forming fully silicided gate electrodes and unsilicided poly resistors
    8.
    发明授权
    Method for forming fully silicided gate electrodes and unsilicided poly resistors 失效
    完全硅化的栅电极和无硅多晶硅电阻的形成方法

    公开(公告)号：US07622345B2

    公开(公告)日：2009-11-24

    申请号：US11254226

    申请日：2005-10-18

    申请人： Steve Ming Ting ,  Chih-Hao Wang

    发明人： Steve Ming Ting ,  Chih-Hao Wang

    IPC分类号： H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L21/28097 ,  H01L21/823443 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/7833

    摘要： A method is disclosed for forming silicided gate electrodes and unsilicided poly resistors. After patterning a semiconductor material for the gate electrode and resistor structures, a first dielectric layer is used to protect a poly resistor that is not to be silicided, then a first silicidation is performed for partially siliciding the gate electrode of the transistor. If the gate electrode is thick, a second dielectric layer is used to protect the resistor that is not to be silicided, then a second silicidation is performed for fully siliciding the gate electrode.

    摘要翻译： 公开了一种用于形成硅化栅电极和非硅化多晶硅电阻器的方法。 在图案化用于栅电极和电阻器结构的半导体材料之后，使用第一介电层来保护不被硅化的多晶硅电阻，然后执行第一硅化以部分地硅化晶体管的栅电极。 如果栅电极较厚，则使用第二电介质层来保护不被硅化的电阻器，然后执行第二次硅化以完全硅化栅电极。

    Nitrogen treatment to improve high-k gate dielectrics
    9.
    发明授权
    Nitrogen treatment to improve high-k gate dielectrics 有权
    氮处理改善高k栅极电介质

    公开(公告)号：US07564108B2

    公开(公告)日：2009-07-21

    申请号：US11115932

    申请日：2005-04-27

    申请人： Chih-Hao Wang ,  Ta-Wei Wang ,  Shang-Chih Chen ,  Ching-Wei Tsai

    发明人： Chih-Hao Wang ,  Ta-Wei Wang ,  Shang-Chih Chen ,  Ching-Wei Tsai

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/76829 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.

    摘要翻译： 公开了具有氮化栅极电介质的MOSFET及其制造。 该方法包括提供衬底并在衬底上沉积非高k电介质材料。 非高k电介质包括两层。 与衬底相邻的第一层基本上是无氮的，第二层包括约1015个原子/ cm3到约1022个原子/ cm3的氮。 MOSFET还包括在氮化的非高k电介质上的高k电介质材料。 高k电介质优选包括HfSiON，ZrSiON或氮化Al 2 O 3。 实施例还包括其中核心和外围集成电路区域被分开优化的不对称制造技术。

    High Performance Transistor with a Highly Stressed Channel
    10.
    发明申请
    High Performance Transistor with a Highly Stressed Channel 有权
    具有高度通道的高性能晶体管

    公开(公告)号：US20080087892A1

    公开(公告)日：2008-04-17

    申请号：US11950467

    申请日：2007-12-05

    申请人： Chih-Hao Wang ,  Ching-Wei Tsai ,  Ta-Wei Wang

    发明人： Chih-Hao Wang ,  Ching-Wei Tsai ,  Ta-Wei Wang

    IPC分类号： H01L29/778 ,  H01L29/04

    CPC分类号： H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

    摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

    摘要翻译： 提供具有高应力沟道区的MOS晶体管及其形成方法。 该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层 第二半导体板。 第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。 该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻 停止层。 在通道区域产生高应力。 由于硅化物区域的增加，电流拥挤效应降低。