-
公开(公告)号：US20130249603A1
公开(公告)日：2013-09-26
申请号：US13991881
申请日：2011-09-29
IPC分类号： H03K5/00
CPC分类号： H03K5/00 , G09G3/3648 , G09G2300/0408 , G09G2300/0819 , G09G2310/0291 , H03K19/018571 , H03K19/018578 , H03K19/0948 , H03K19/09482
摘要： Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.
摘要翻译： 这里描述的是用于减小晶体管的电应力过大以及为负载独立缓冲器产生具有确定性占空比的输出的装置，系统和方法。 该装置包括电耦合在缓冲器的输入端子和输出端子之间的反馈电容器; 以及与所述反馈电容器电并联并且可操作以响应于控制信号使所述反馈电容器电短路的开关，其中所述开关导致所述输入端子上的确定性电压电平。
-
公开(公告)号：US09509292B2
公开(公告)日：2016-11-29
申请号：US13991881
申请日：2011-09-29
IPC分类号： H03K3/00 , H03K5/00 , H03K19/0185 , H03K19/0948
CPC分类号： H03K5/00 , G09G3/3648 , G09G2300/0408 , G09G2300/0819 , G09G2310/0291 , H03K19/018571 , H03K19/018578 , H03K19/0948 , H03K19/09482
摘要： Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.
摘要翻译： 这里描述的是用于减小晶体管的电应力过大以及为负载独立缓冲器产生具有确定性占空比的输出的装置，系统和方法。 该装置包括电耦合在缓冲器的输入端子和输出端子之间的反馈电容器; 以及与所述反馈电容器电并联并且可操作以响应于控制信号使所述反馈电容器电短路的开关，其中所述开关导致所述输入端子上的确定性电压电平。
-
公开(公告)号：US20160241244A1
公开(公告)日：2016-08-18
申请号：US15135482
申请日：2016-04-21
IPC分类号： H03K19/0948 , G09G3/36 , H03K19/0185
摘要： Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.
-
-
搜索结果
3 条记录 (耗时 0.014 秒)