公开(公告)号：US20140035126A1

公开(公告)日：2014-02-06

申请号：US13562558

申请日：2012-07-31

申请人： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hiu Chen

发明人： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hiu Chen

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

摘要： A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers.

公开(公告)号：US20140010013A1

公开(公告)日：2014-01-09

申请号：US13540803

申请日：2012-07-03

申请人： HSIAO-HUA LU ,  CHIH-MING KUO ,  YU-CHUN WANG

发明人： HSIAO-HUA LU ,  CHIH-MING KUO ,  YU-CHUN WANG

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/16

摘要： A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.

摘要翻译： 引入存储器擦除方法及其驱动电路，当选择要擦除单元时，该方法包括设置未被选择被擦除且位于所选块的单元的门，所选择的单元的所有单元的漏极 银行，未选择的单元格的门将浮动; 为所选择的银行的所有来源提供正电压及其共享的P阱和N阱; 并向位于所选块中的单元的栅极提供负电压并选择被擦除。 因此，每当门浮动时，都接收来自P阱的正耦合电压，以便禁止未选择的块的擦除，从而简化解码，从而使得容易实现具有小布局面积和扇区划分的块或块的进一步扩展 在街区。

公开(公告)号：US20130334671A1

公开(公告)日：2013-12-19

申请号：US13613309

申请日：2012-09-13

申请人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

发明人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

IPC分类号： H01L23/495

CPC分类号： H01L24/16 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

摘要翻译： 半导体封装包括引线框架，至少一个芯片和模塑料。 引线框架包括多个引线，每个引线包括第一端部部分和至少一个联接突出部分，其中第一端部部分包括第一上表面，联接突出部包括环形表面，并且一体地形成为与第 第一上表面。 设置在引线顶部的芯片包括多个凸块和多个焊料，耦合突起嵌入焊料中以使耦合突起的环表面被焊料包覆。 焊料覆盖第一个上表面。 芯片和引线用模塑料包覆。

公开(公告)号：US20130249070A1

公开(公告)日：2013-09-26

申请号：US13426804

申请日：2012-03-22

申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

摘要： A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

摘要翻译： 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

公开(公告)号：US20130183823A1

公开(公告)日：2013-07-18

申请号：US13352537

申请日：2012-01-18

申请人： Chih-Ming Kuo ,  Hua-An Dai ,  Cheng-Fan Lin ,  Yie-Chuan Chiu ,  Yung-Wei Hsieh

发明人： Chih-Ming Kuo ,  Hua-An Dai ,  Cheng-Fan Lin ,  Yie-Chuan Chiu ,  Yung-Wei Hsieh

IPC分类号： H01L21/60

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05552

摘要： A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer.

摘要翻译： 凸起工艺包括提供硅衬底，在硅衬底上形成含钛金属层，其中含钛金属层包括多个第一区域和多个第二区域，在含钛金属层上形成光致抗蚀剂层 金属层，图案化光致抗蚀剂层以形成对应于含钛金属层的第一区域的多个开口槽，在开口槽处形成多个铜凸块，进行热程序，形成多个凸块隔离层 在铜凸块上，在凸块隔离层上形成多个连接层，去除光致抗蚀剂层，去除第二区域，并且使得每个第一区域能够形成凸起下的冶金层。

公开(公告)号：US20130075860A1

公开(公告)日：2013-03-28

申请号：US13247076

申请日：2011-09-28

申请人： Chih-Ming Kuo ,  You-Ming Hsu

发明人： Chih-Ming Kuo ,  You-Ming Hsu

IPC分类号： H01L23/48 ,  H01L21/02

CPC分类号： H01L23/48 ,  H01F5/00 ,  H01F5/003 ,  H01F17/0033 ,  H01F41/046 ,  H01L28/10

摘要： A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

摘要翻译： 制造电感器载体的方法包括以下步骤：提供具有保护层的衬底; 在保护层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成第一开口和第一孔; 在第一开口和第一孔内形成第一金属层; 去除第一光致抗蚀剂层; 在保护层上形成第一介电层; 在第一介电层上形成第二光致抗蚀剂层; 图案化第二光致抗蚀剂层以形成第二孔和多个第三孔; 在第二孔和第三孔内形成第二金属层; 去除所述第二光致抗蚀剂层; 在第一介电层上形成第二电介质层; 在第二介电层上形成第三光致抗蚀剂层; 图案化第三光致抗蚀剂层以形成第五孔和第六孔; 在第五孔径和第六孔内形成第三金属层。

公开(公告)号：US20130002387A1

公开(公告)日：2013-01-03

申请号：US13173022

申请日：2011-06-30

申请人： Chih-Ming Kuo ,  You-Ming Hsu

发明人： Chih-Ming Kuo ,  You-Ming Hsu

IPC分类号： H01F5/00 ,  H05K3/10

CPC分类号： H01F5/00 ,  H01F5/003 ,  H05K1/165 ,  H05K3/465 ,  H05K2201/097 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49155

摘要： A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

公开(公告)号：US20100014353A1

公开(公告)日：2010-01-21

申请号：US12174094

申请日：2008-07-16

申请人： Hsiao-Hua Lu ,  Chih-Ming Kuo

发明人： Hsiao-Hua Lu ,  Chih-Ming Kuo

IPC分类号： G11C16/04

CPC分类号： G11C7/1045 ,  G11C5/066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105

摘要： In a flash memory device with switching I/O structure for applying in flash memory products, depending on actual need for input and/or output pins, other pins may be flexibly switched to input, output, or bi-directional pins through software and/or hardware and/or CAM access. Therefore, data input and/or output rate may be changed through switching the I/O structure. Moreover, after the I/O configuration, the switched other pins may start data input/output immediately after the flash memory is started to operate, without the need of waiting for several input/output phases.

摘要翻译： 在具有用于应用于闪速存储器产品中的开关I / O结构的闪速存储器件中，根据输入和/或输出引脚的实际需要，其他引脚可以通过软件和/或引脚灵活地切换到输入，输出或双向引脚， 或硬件和/或CAM访问。 因此，可以通过切换I / O结构来改变数据输入和/或输出速率。 此外，在I / O配置之后，切换的其他引脚可以在闪存开始运行之后立即开始数据输入/输出，而不需要等待多个输入/输出阶段。

公开(公告)号：US20050073328A1

公开(公告)日：2005-04-07

申请号：US10822524

申请日：2004-04-12

申请人： Shun-Chi Huang ,  Chih-Ming Kuo

发明人： Shun-Chi Huang ,  Chih-Ming Kuo

IPC分类号： G01R31/28 ,  G01R31/00

CPC分类号： G01R31/2841

摘要： Methods and apparatus for testing a semiconductor structure requiring a precise core or operating voltage with an OBIRCH analysis arrangement. The separate power supply used for providing the precise core or operating voltage is eliminated, and is replaced by connecting a circuit comprised of a plurality of Schottky diodes connected in series across the constant voltage power supply used to provide the current for the OBIRCH analysis. A precise voltage is then tapped from an anode of the series connected Schottky diodes thereby significantly reducing effects of background noise on the OBIRCH analysis.

摘要翻译： 使用OBIRCH分析装置测试需要精确磁芯或工作电压的半导体结构的方法和装置。 用于提供精确磁芯或工作电压的单独的电源被消除，并且通过连接包括串联连接的多个肖特基二极管的电路来代替，该电路用于提供用于OBIRCH分析的电流的恒压电源。 然后从串联的肖特基二极管的阳极上抽出精确的电压，从而显着降低背景噪声对OBIRCH分析的影响。

公开(公告)号：US06753195B2

公开(公告)日：2004-06-22

申请号：US10449008

申请日：2003-06-02

申请人： Chih-Ming Kuo

发明人： Chih-Ming Kuo

IPC分类号： H01L2166

CPC分类号： H01L51/56 ,  H01L2251/568

摘要： A method of repairing organic light-emitting element pixels for repairing an organic light-emitting element having a substantial short circuit portion or portions. The method includes an electrical testing step and an insulator-forming step. The organic light-emitting element includes an anode substrate, an organic functional layer and a cathode. In this case, a current or voltage is applied to the anode substrate and the cathode of the organic light-emitting element respectively in the electrical testing step, so that the short circuit portion or portions of the organic light-emitting element are transformed to an open circuit portion or portions. In the insulator-forming step, an insulator is formed at the open circuit portion or portions of the organic light-emitting element. The invention also discloses a method of repairing organic light-emitting element pixels, which further includes an electrical detection step. A short-circuit level of the organic light-emitting element is detected in the electrical detection step. When the ratio of the amount of the short circuit portions to the amount of the open circuit portions is less than a predetermined value, the insulator is formed on the open circuit portions in the subsequent insulator-forming step.

摘要翻译： 修复有机发光元件像素以修复具有实质上短路部分的有机发光元件的方法。 该方法包括电测试步骤和绝缘体形成步骤。 有机发光元件包括阳极基板，有机功能层和阴极。 在这种情况下，在电气测试步骤中分别向阳极衬底和有机发光元件的阴极施加电流或电压，使得有机发光元件的短路部分或部分转变为 开路部分。 在绝缘体形成工序中，在有机发光元件的开路部或部分形成有绝缘体。 本发明还公开了一种修复有机发光元件像素的方法，其还包括电检测步骤。 在电检测步骤中检测出有机发光元件的短路电平。 当短路部分的量与开路部分的量的比例小于预定值时，在随后的绝缘体形成步骤中的开路部分上形成绝缘体。