利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

123 条记录 (耗时 0.051 秒)

    Signal amplification circuits for receiving/transmitting signals according to input signal
    3.
    发明授权
    Signal amplification circuits for receiving/transmitting signals according to input signal 有权
    用于根据输入信号接收/发送信号的信号放大电路

    公开(公告)号：US08310314B2

    公开(公告)日：2012-11-13

    申请号：US12876237

    申请日：2010-09-06

    申请人： Chih-Hung Lee

    发明人： Chih-Hung Lee

    IPC分类号： H03F3/68

    CPC分类号： H03F1/223 ,  H03F1/0277 ,  H03F1/565 ,  H03F3/189 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/68 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/405 ,  H03F2200/534 ,  H03F2203/45481

    摘要： One exemplary signal amplification circuit used for processing an input signal includes an input stage, a plurality of output stages, and a selecting stage. The input stage has an input node for receiving the input signal and an output node for outputting an intermediate signal. The output stages are coupled to a plurality of output ports of the signal amplification circuit, respectively. Each of the output stages generates a corresponding processed signal to a corresponding output port according to a gain and a signal derived from the intermediate signal of the input stage when enabled. The selecting stage is arranged for selectively coupling the output node of the input stage to at least one of the output stages.

    摘要翻译： 用于处理输入信号的一个示例性信号放大电路包括输入级，多个输出级和选择级。 输入级具有用于接收输入信号的输入节点和用于输出中间信号的输出节点。 输出级分别与信号放大电路的多个输出端口耦合。 每个输出级根据增益和从输入级的中间信号导出的信号在使能时产生对应的输出端口的相应处理信号。 选择级被布置成选择性地将输入级的输出节点耦合到至少一个输出级。

    Clock data recovery circuit
    7.
    发明授权
    Clock data recovery circuit 有权
    时钟数据恢复电路

    公开(公告)号：US07983361B2

    公开(公告)日：2011-07-19

    申请号：US11957561

    申请日：2007-12-17

    申请人： Shen-Iuan Liu ,  Chih-Hung Lee ,  Lan-Chou Cho

    发明人： Shen-Iuan Liu ,  Chih-Hung Lee ,  Lan-Chou Cho

    IPC分类号： H04L27/00

    CPC分类号： H04L7/033 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0084 ,  H03L7/0805 ,  H03L7/18 ,  H04L7/0338

    摘要： A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.

    摘要翻译： 时钟数据恢复电路。 时钟数据恢复电路包括传输线，锁相环，压控振荡器，相位选择器和D触发器。 传输线接收输入信号。 锁相环通过传输线和参考时钟接收输入信号并产生第一时钟信号。 压控振荡器通过传输线接收输入信号，并从锁相环的内部节点接收控制电压，并产生时钟信号。 相位选择器通过传输线接收输入信号和来自压控振荡器的时钟信号，并产生时钟输出信号。 D触发器经由传输线和时钟输出信号接收输入信号，并产生数据输出信号。

    Limiting amplifiers
    9.
    发明授权
    Limiting amplifiers 有权
    限幅放大器

    公开(公告)号：US07902900B2

    公开(公告)日：2011-03-08

    申请号：US12613794

    申请日：2009-11-06

    申请人： Shen-luan Liu ,  Chih-Hung Lee

    发明人： Shen-luan Liu ,  Chih-Hung Lee

    IPC分类号： H03L5/00 ,  H03F3/45

    CPC分类号： H03F3/08 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/258 ,  H03F2203/45638

    摘要： A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

    摘要翻译： 具有直流失调消除输入级的限幅放大器，相同的增益级，输出缓冲器和反馈滤波器。 输入级接收差分输入信号并输出​​第一中间差分信号。 增益级级联以放大第一中间差分信号并产生第二中间差分信号，由输出缓冲器放大以产生输出信号。 反馈滤波器为直流偏移消除提供输出级的输出信号的直流失调电压。 输入级包括耦合在一对输入节点和电源线之间并包括公共电阻器，一对负载电阻器和分流电阻器的电阻器网络。 负载电阻共用连接到与电源线相连的公共电阻的公共端子。 分流电阻有两个端子分别连接到负载电阻。