Semiconductor devices, transistors, and methods of manufacture thereof
    2.
    发明授权
    Semiconductor devices, transistors, and methods of manufacture thereof 有权
    半导体器件,晶体管及其制造方法

    公开(公告)号:US08883583B2

    公开(公告)日:2014-11-11

    申请号:US13533749

    申请日:2012-06-26

    Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

    Abstract translation: 公开了半导体器件,晶体管及其制造方法。 在一个实施例中,半导体器件包括设置在工件上方的栅极电介质,设置在栅极电介质上方的栅极和设置在栅极和栅极电介质的侧壁上的间隔物。 源极区域设置在栅极的第一侧附近的间隔物处,并且漏极区域设置在栅极的第二侧上靠近隔离物的位置。 金属层设置在源极区域和漏极区域上。 金属层在间隔物下方延伸约25%或更大于间隔物的宽度。

    STRUCTURE OF CONNECTOR
    3.
    发明申请
    STRUCTURE OF CONNECTOR 审中-公开
    连接器结构

    公开(公告)号:US20120244744A1

    公开(公告)日:2012-09-27

    申请号:US13053198

    申请日:2011-03-21

    Inventor: CHING-KUN HUANG

    CPC classification number: H01R13/521 H01R24/542

    Abstract: A connector structure includes a coaxial cable coupler, which receives therein at least one positioning block. The positioning block has a surface against which a water seal pad is positioned. A conductive pin is arranged to extend through the positioning block and the water seal pad. As such, the arrangement of the water seal pad effectively prevents invasion of water and simplifies the assembling process to thereby reduce the assembling costs.

    Abstract translation: 连接器结构包括同轴电缆耦合器,其中接收至少一个定位块。 定位块具有一个表面,水密封垫定位在该表面上。 导电销布置成延伸穿过定位块和水封垫。 因此,水封垫的布置有效地防止了水的侵入并且简化了组装过程,从而降低了组装成本。

    Coaxial cable terminal
    4.
    发明授权
    Coaxial cable terminal 有权
    同轴电缆端子

    公开(公告)号:US07896695B1

    公开(公告)日:2011-03-01

    申请号:US12628750

    申请日:2009-12-01

    Inventor: Ching-Kun Huang

    CPC classification number: H01R13/111 H01R13/46

    Abstract: A coaxial cable terminal includes an insulating shell and a connection terminal. An interior of the insulating shell is hollow and is thus formed with a holding space. Two ends of the insulating shell are provided respectively with an opening. The connection terminal is accommodated in the holding space and is extended toward one end to form at least two leaves. Each leaf is first bent inward with an abutting section and a tail end of the abutting section is then bent outward to extend with a contact section. A bonding end is formed between the abutting section and the contact section. When a coaxial cable terminal is inserted, the coaxial cable terminal is clamped by the bonding end and is bonded by elastic abutting of the abutting section. Therefore, the present invention can be compatible with the coaxial cables of various apertures and will not be elastically fatigue easily.

    Abstract translation: 同轴电缆端子包括绝缘外壳和连接端子。 绝缘壳体的内部是中空的,因此形成有保持空间。 绝缘壳的两端分别设有开口。 连接端子容纳在保持空间中并且朝向一端延伸以形成至少两个叶。 首先,每个叶片首先向内弯曲,并且邻接部分的尾端然后向外弯曲以与接触部分一起延伸。 接合端部形成在抵接部与接触部之间。 当插入同轴电缆端子时,同轴电缆端子被接合端夹紧,并通过邻接部分的弹性抵接而结合。 因此,本发明可以与各种孔的同轴电缆兼容,并且不会容易地弹性疲劳。

    Stagger memory cell array
    6.
    发明申请
    Stagger memory cell array 有权
    交错记忆单元阵列

    公开(公告)号:US20070272985A1

    公开(公告)日:2007-11-29

    申请号:US11441646

    申请日:2006-05-25

    CPC classification number: H01L27/0207 H01L27/11

    Abstract: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.

    Abstract translation: 存储器件包括具有第一锁存区域的第一存储器单元区域,其中一个或多个电子元件被构造用于存储值,以及围绕第一锁存区域的第一周边区域; 并且第二存储单元区域被布置为与第一存储单元区域的第一侧相邻,并且具有第二锁存区域,其中一个或多个电子元件被构造用于存储值,以及围绕第二锁存区域的第二周边区域。 第一存储单元区域的一个边缘从其对应的第二存储单元区域的边缘移开。 因此,可以调整存储装置的面积或产量。

    STRUCTURE OF CONNECTOR
    7.
    发明申请
    STRUCTURE OF CONNECTOR 审中-公开
    连接器结构

    公开(公告)号:US20120252269A1

    公开(公告)日:2012-10-04

    申请号:US13072790

    申请日:2011-03-28

    Inventor: CHING-KUN HUANG

    CPC classification number: H01R13/502

    Abstract: An improved structure of connector includes a sheath and a conductive terminal that is received in the sheath. The sheath includes first and second sheath members. The first sheath member has an end forming a flange and an opposite end forming a plurality of elastic segments. The second sheath member forms a receiving chamber in which the first sheath member is receivable and also forms, inside an end thereof, a positioning section on which the elastic segments are positionable. As such, when an external terminal pin is inserted into the second sheath member to engage the conductive terminal, the positioning section retains the elastic segments in position to prevent the insertion of the external terminal pin from being made in an incorrect, deviated direction and thus damaging the conductive terminal. The arrangement of the elastic segments provides the conductive terminal with better capability of bearing external damages.

    Abstract translation: 连接器的改进的结构包括护套和容纳在护套中的导电端子。 护套包括第一和第二护套构件。 第一护套构件具有形成凸缘的端部和形成多个弹性段的相对端部。 第二护套构件形成容纳室,其中第一护套构件可接收,并且在其一端形成弹性区段可定位的定位区段。 这样,当将外部端子销插入到第二护套构件中以接合导电端子时,定位部将弹性区段保持在适当位置,以防止外部端子插头插入不正确的偏离方向,因此 损坏导电端子。 弹性段的布置为导电端子提供了更好的承受外部损坏的能力。

    INTEGRATED CIRCUIT HAVING THINNER GATE DIELECTRIC AND METHOD OF MAKING
    9.
    发明申请
    INTEGRATED CIRCUIT HAVING THINNER GATE DIELECTRIC AND METHOD OF MAKING 有权
    具有薄壁电介质的集成电路及其制造方法

    公开(公告)号:US20130207200A1

    公开(公告)日:2013-08-15

    申请号:US13371168

    申请日:2012-02-10

    CPC classification number: H01L21/823462

    Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.

    Abstract translation: 一种集成电路,包括具有第一厚度的第一栅极介电层的第一晶体管。 集成电路还包括具有第二厚度的第二栅介质层的第二晶体管,并且第二晶体管被配置为电连接到第一晶体管。 集成电路还包括具有第三厚度的第三栅极电介质层的第三晶体管,并且第三晶体管被配置为电连接到第一晶体管或第二晶体管中的至少一个晶体管。 集成电路的第一厚度,第二厚度和第三厚度都是不同的。

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