公开(公告)号：US08854897B2

公开(公告)日：2014-10-07

申请号：US13665941

申请日：2012-11-01

Applicant: Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

Inventor： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

IPC: G11C7/10

CPC classification number: G11C11/413

Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

Abstract translation: 静态随机存取存储装置和位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

公开(公告)号：US20130194861A1

公开(公告)日：2013-08-01

申请号：US13562330

申请日：2012-07-31

Applicant: Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

Inventor： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

Abstract translation: 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

公开(公告)号：US08320164B2

公开(公告)日：2012-11-27

申请号：US12985289

申请日：2011-01-05

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C11/00

CPC classification number: G11C11/419

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract translation: 一种具有数据控制电源的静态随机存取存储器，其包括存储单元电路和至少一个写辅助电路，用于根据要写入存储单元电路的数据向存储单元电路供电。

公开(公告)号：US08213257B2

公开(公告)日：2012-07-03

申请号：US12852759

申请日：2010-08-09

Applicant: Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract translation: 提供随机存取存储器（RAM）。 RAM包括多个字线驱动器，至少第一跟踪晶体管和第二跟踪晶体管。 每个字线驱动器具有接收解码信号的输入节点，接收操作电压的功率节点和驱动字线的驱动节点。 在一个实施例中，第一跟踪晶体管具有分别耦合到字线驱动器之一的驱动节点和第二跟踪晶体管的通道终端节点的两个通道终端节点; 其中所述第一跟踪晶体管具有跟踪字线驱动器的驱动晶体管的电子特性的电子特性，并且所述第二跟踪晶体管具有跟踪所述RAM的每个单元中的栅极晶体管的电子特性。

公开(公告)号：US20120044779A1

公开(公告)日：2012-02-23

申请号：US13009240

申请日：2011-01-19

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract translation: 提供具有多个单元的随机存取存储器（RAM）。 在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。 每个电池有两个逆变器; 电源控制器有两个电源开关。 对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

公开(公告)号：US20120014171A1

公开(公告)日：2012-01-19

申请号：US12876582

申请日：2010-09-07

Applicant: Ching-Te Chuang ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

Inventor： Ching-Te Chuang ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L29/785

Abstract: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.

Abstract translation: 本发明提供了一种基于施密特触发器的FinFET静态随机存取存储器（SRAM）单元，其是8-FinFET结构。 FinFET具有两个独立门的功能。 与之前的工作中的10-FinFET结构相比，新的SRAM单元仅使用8个FinFET。 结果，本发明的电池结构可以节省芯片面积并提高芯片密度。 此外，这种新的SRAM单元可以有效地解决6T SRAM单元在低工作电压下可能具有读出错误的常规问题。

公开(公告)号：US07876131B2

公开(公告)日：2011-01-25

申请号：US11859351

申请日：2007-09-21

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC: H03K19/20 ,  H03K19/094 ,  H01L21/84

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract translation: 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

公开(公告)号：US07362606B2

公开(公告)日：2008-04-22

申请号：US11392071

申请日：2006-03-29

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract translation: 为非对称SRAM单元提供技术，例如可通过提供改进的读取稳定性和改进的写入性能和余量来提供一个或多个。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

公开(公告)号：US07323908B2

公开(公告)日：2008-01-29

申请号：US11260571

申请日：2005-10-27

Applicant: Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

Inventor： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC: H03K19/0175 ,  H03K19/094 ,  H03K3/03

CPC classification number: G01R31/31725

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract translation: 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US07313012B2

公开(公告)日：2007-12-25

申请号：US11362613

申请日：2006-02-27

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.