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公开(公告)号：US20160284639A1
公开(公告)日：2016-09-29
申请号：US14856469
申请日：2015-09-16
发明人： SHENG-PAI CHEN
IPC分类号： H01L23/528 , H01L23/00
CPC分类号： H01L23/528 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L24/02 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0235 , H01L2224/02351 , H01L2224/0239 , H01L2224/0401 , H01L2224/05548 , H01L2224/05551 , H01L2224/05557 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/1191 , H01L2224/13024 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/132 , H01L2224/13299 , H01L2924/351 , H01L2924/3512 , H01L2924/35121 , H01L2924/00012 , H01L2924/01022 , H01L2924/01029 , H01L2924/01079 , H01L2924/01028 , H01L2924/014 , H01L2924/00014
摘要： The present disclosure relates to a semiconductor structure, which includes a semiconductor substrate, an insulating layer and a plurality of wirings. The insulating layer is disposed on the semiconductor substrate. The plurality of wirings are disposed between the semiconductor substrate and the insulating layer. At least one wiring of the wirings includes a plurality of holes, and a total area of the holes is from 10% to 70% of a surface area of the at least one wiring.
摘要翻译： 本公开涉及一种半导体结构，其包括半导体衬底，绝缘层和多个布线。 绝缘层设置在半导体衬底上。 多个布线设置在半导体衬底和绝缘层之间。 布线的至少一个布线包括多个孔，并且孔的总面积为至少一个布线的表面积的10％至70％。
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公开(公告)号：US20040035706A1
公开(公告)日：2004-02-26
申请号：US10223350
申请日：2002-08-20
发明人： S. J. Cheng , An-Hong Liu , Yeong-Her Wang , Yuan-Ping Tseng , Y. J. Lee
IPC分类号： C25D005/00
CPC分类号： C25D5/022 , C25D5/04 , G01R1/07342 , G01R3/00 , H05K3/241 , H05K3/4007 , H05K2201/0367
摘要： A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.
摘要翻译： 探针卡的探针的方法包括在电镀槽上设置阻挡板。 阻挡板根据探针头上的接触垫的布局具有多个开口。 探针头的接触垫上有凹凸。 凸点（接触垫）可以通过阻挡板的开口接触电镀槽中的电镀溶液，进行连续电镀工艺。 通过根据所需形状的探针连续移动探头，通过电镀形成探针。 这些探针可以制成不同的形状，具有良好的弹性和高度均匀性，以提高晶片探测期间电接触的质量。 此外，节省了处理时间和制造成本。
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公开(公告)号：US20160240500A1
公开(公告)日：2016-08-18
申请号：US14845826
申请日：2015-09-04
发明人： CHUN FU HUANG
CPC分类号： H01L24/13 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L2224/02373 , H01L2224/0345 , H01L2224/03452 , H01L2224/03622 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/11418 , H01L2224/1145 , H01L2224/11462 , H01L2224/13016 , H01L2224/13076 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13184 , H01L2924/0132 , H01L2924/0133 , H01L2924/2064 , H01L2924/00014 , H01L2924/013 , H01L2924/01074 , H01L2924/01029 , H01L2924/01024 , H01L2924/014 , H01L2924/0105 , H01L2924/01079 , H01L2924/01047
摘要： A packaged semiconductor device is provided, which includes a substrate comprising a contact pad; a passivation layer disposed on the substrate, where the passivation layer covers part of the contact pad; an under bump metallization (UBM) layer disposed on the substrate, where the UBM layer is coupled to the contact pad; a conductive bump disposed on the UBM layer, where the conductive bump comprises a column connecting the UBM layer and a cap disposed on top of the column; and a solder ball encapsulating the conductive bump. The cap includes a bottom area larger than a cross-sectional area of the column, and a bottom of the cap is distant from an upper surface of the passivation layer by a space.
摘要翻译： 提供了一种封装的半导体器件，其包括包括接触焊盘的衬底; 设置在所述基板上的钝化层，其中所述钝化层覆盖所述接触焊盘的一部分; 设置在所述衬底上的凹凸金属化（UBM）层，其中所述UBM层耦合到所述接触焊盘; 布置在所述UBM层上的导电凸块，其中所述导电凸块包括连接所述UBM层和设置在所述柱顶部上的盖的柱; 以及封装导电凸块的焊球。 盖包括大于柱的横截面面积的底部区域，并且盖的底部与钝化层的上表面间隔一个空间。
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4.发明授权公开(公告)号：US09728479B2
公开(公告)日：2017-08-08
申请号：US14856546
申请日：2015-09-16
发明人： Shih-Wen Chou
IPC分类号： H01L23/31 , H01L25/00 , H01L21/56 , H01L25/065 , H01L23/00
CPC分类号： H01L23/3157 , H01L21/561 , H01L21/563 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/1403 , H01L2224/16147 , H01L2224/16227 , H01L2224/1703 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/83385 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2224/83 , H01L2224/81 , H01L2224/03 , H01L2224/11
摘要： A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.
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公开(公告)号：US20160329269A1
公开(公告)日：2016-11-10
申请号：US14874486
申请日：2015-10-05
发明人： Chi-Jin Shih
IPC分类号： H01L23/495 , H01L21/56 , H01L23/31
CPC分类号： H01L23/49548 , H01L23/3107 , H01L23/4951 , H01L23/49582 , H01L24/00 , H01L2021/60022 , H01L2224/16245 , H01L2924/181 , H01L2924/00012
摘要： A chip package structure including a lead frame, a chip, a plurality of solder bumps, a solder resist layer and an encapsulant is provided. The lead frame has a plurality of inner leads. Each of the inner leads has an upper surface, a lower surface, two side surfaces opposite to each other and a bonding area on the upper surface. The chip is disposed on the lead frame and has an active surface. Each of the solder bumps connects the active surface and the bonding area of each of the inner leads. The solder resist layer is disposed on at least one of the lower surface or the two side surfaces of each of the inner leads. The encapsulant covers the lead frame, the chip, the solder bumps and the solder resist layer. A manufacturing method of the chip package structure is also provided.
摘要翻译： 提供了包括引线框架，芯片，多个焊料凸块，阻焊层和密封剂的芯片封装结构。 引线框架具有多个内引线。 每个内引线具有上表面，下表面，彼此相对的两个侧表面和上表面上的接合区域。 芯片设置在引线框架上并具有有源表面。 每个焊料凸点连接每个内引线的有源表面和接合区域。 阻焊层设置在每个内引线的下表面或两个侧表面中的至少一个上。 密封剂覆盖引线框架，芯片，焊料凸块和阻焊层。 还提供了芯片封装结构的制造方法。
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6.发明申请公开(公告)号：US20160315067A1
公开(公告)日：2016-10-27
申请号：US14855397
申请日：2015-09-16
发明人： Shih-Wen Chou
IPC分类号： H01L25/065 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3142 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/1403 , H01L2224/14131 , H01L2224/14179 , H01L2224/16147 , H01L2224/16227 , H01L2224/1703 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/83385 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2224/11 , H01L2224/81 , H01L2224/03 , H01L2224/83
摘要： A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.
摘要翻译： 多芯片封装结构包括第一芯片，至少一个阻挡结构，多个第一导电凸块，第二芯片，多个第二导电凸块和底部填充。 第一芯片具有芯片连接区域，芯片连接区域中的多个第一内部焊盘和芯片连接区域外部的多个第一外部焊盘。 阻挡结构设置在第一内垫和第一外垫之间并且包围第一内垫。 第一导电凸块设置在第一外垫上。 第二芯片在芯片连接区域上翻转并具有多个第二焊盘。 第二导电凸块设置在第一内垫和第二垫之间。 底部填充物设置在第一芯片和第二芯片之间，以覆盖第二导电凸块。
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7.发明申请公开(公告)号：US20150347806A1
公开(公告)日：2015-12-03
申请号：US14477870
申请日：2014-09-05
发明人： Li-Chun Li , Chia-I Tsai
CPC分类号： H01L24/81 , G06K9/00013 , H01L21/563 , H01L23/4985 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/83851 , H01L2224/92125 , H01L2924/00014 , H01L2924/07025 , H01L2924/07802 , H01L2924/0781 , H01L2924/1579 , H01L2924/00 , H01L2224/13099
摘要： A chip package structure includes a flexible substrate, a patterned circuit layer, a fingerprint sensor chip, a plurality of bumps, a patterned dielectric layer and an encapsulant layer. The patterned circuit layer disposed on the flexible substrate includes a fingerprint sensing circuit and a plurality of terminals. The fingerprint sensor chip disposed on the flexible substrate is electrically connected to the fingerprint sensing circuit and includes an active surface, a back surface, and a plurality of bonding pads disposed on the active surface. The bumps disposed between the fingerprint sensor chip and the patterned circuit layer electrically connect the bonding pads and the terminals. The patterned dielectric layer including a first surface and a second surface having a fingerprint sensing region at least covers the fingerprint sensing circuit with the first surface. The encapsulant layer is filled between the flexible substrate and the fingerprint sensor chip and covers the bumps.
摘要翻译： 芯片封装结构包括柔性衬底，图案化电路层，指纹传感器芯片，多个凸块，图案化电介质层和密封剂层。 设置在柔性基板上的图案化电路层包括指纹感测电路和多个端子。 设置在柔性基板上的指纹传感器芯片电连接到指纹感测电路，并且包括有源表面，后表面和设置在有源表面上的多个接合焊盘。 布置在指纹传感器芯片和图案化电路层之间的凸起电连接接合焊盘和端子。 包括具有指纹感测区域的第一表面和第二表面的图案化电介质层至少覆盖具有第一表面的指纹感测电路。 密封剂层填充在柔性基板和指纹传感器芯片之间并覆盖凸块。
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公开(公告)号：US09653429B2
公开(公告)日：2017-05-16
申请号：US14855397
申请日：2015-09-16
发明人： Shih-Wen Chou
IPC分类号： H01L25/065 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/563 , H01L21/78 , H01L23/3142 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/1403 , H01L2224/14131 , H01L2224/14179 , H01L2224/16147 , H01L2224/16227 , H01L2224/1703 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/83385 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2224/11 , H01L2224/81 , H01L2224/03 , H01L2224/83
摘要： A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.
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9.发明申请公开(公告)号：US20160315028A1
公开(公告)日：2016-10-27
申请号：US14856546
申请日：2015-09-16
发明人： Shih-Wen Chou
IPC分类号： H01L23/31 , H01L25/00 , H01L21/56 , H01L25/065
CPC分类号： H01L23/3157 , H01L21/561 , H01L21/563 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/1403 , H01L2224/16147 , H01L2224/16227 , H01L2224/1703 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/83385 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2224/83 , H01L2224/81 , H01L2224/03 , H01L2224/11
摘要： A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.
摘要翻译： 多芯片封装结构包括第一芯片，第二芯片，电路层，多个第一导电凸块，多个第二导电凸块和底部填充。 第一芯片具有芯片接合区域，多个第一内部焊盘和第一外部焊盘。 电路层设置在第一芯片上，并且包括多个绝缘层和至少一个金属层。 绝缘层具有设置在第一内垫和第一外垫之间并围绕第一内垫的槽。 第一导电凸块设置在第一外垫上。 第二芯片在芯片接合区域翻转。 每个第一内垫通过第二导电凸块电连接到第二芯片的第二垫。 底部填充物设置在第一和第二芯片之间并且覆盖第二导电凸块。
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公开(公告)号：US20040012405A1
公开(公告)日：2004-01-22
申请号：US10198119
申请日：2002-07-19
发明人： S. J. Cheng , An-Hong Liu , Yeong-Her Wang , Yuan-Ping Tseng , Y. J. Lee
IPC分类号： G01R031/02
CPC分类号： G01R1/07378 , G01R3/00
摘要： A probe card with full wafer contact configuration comprises a back plate and a plurality of modular multiplayer ceramic wiring boards coplanarly mounted on the back plate. The total size of the modular multilayer ceramic wiring boards is larger than that of a wafer under test in order to fully contact all the bonding pads of the wafer under test. The modular multilayer ceramic wiring boards can be manufactured separately according to various locations. Thus, the manufacturing cost is reduced and yield is improved and lead time is shortened.
摘要翻译： 具有全晶片接触构造的探针卡包括背板和共面安装在背板上的多个模块化多层陶瓷布线板。 模块化多层陶瓷布线板的总尺寸大于被测晶圆的总尺寸，以便完全接触被测晶片的所有焊盘。 模块化多层陶瓷布线板可以根据各种不同的位置分开制造。 因此，制造成本降低，产量提高，交货时间缩短。
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