公开(公告)号：US5567642A

公开(公告)日：1996-10-22

申请号：US554337

申请日：1995-11-06

申请人： Hyeon S. Kim ,  Choong H. Lee

发明人： Hyeon S. Kim ,  Choong H. Lee

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/70

CPC分类号： H01L21/28061 ,  H01L21/823842 ,  H01L27/0928 ,  Y10S148/019

摘要： A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.

摘要翻译： 公开了一种制造CMOS器件的栅电极的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层，第一导电层和保护层; 选择性地蚀刻其中将形成PMOS晶体管的保护层的预定部分; 在所述衬底的整个表面上形成第二导电层; 去除形成在保护层上的第二导电层，并将保护层部分蚀刻到预定厚度; 以及使用栅极电极图案来图案化第二导电层，保护层，第一导电层和栅极绝缘层。