公开(公告)号：US07986582B2

公开(公告)日：2011-07-26

申请号：US12186195

申请日：2008-08-05

申请人： Hermann Ruckerbauer ,  Christian Sichert

发明人： Hermann Ruckerbauer ,  Christian Sichert

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C5/04 ,  G11C8/08 ,  G11C8/14

摘要： A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.

摘要翻译： 一种用于操作包括至少两个存储器设备的存储器设备的方法，每个存储器设备包含至少一个存储体，包括：基于行激活命令激活至少一个存储体中的至少一个字线; 存储银行信息，所述银行信息指示每个存储器设备的哪些存储体包含由行激活命令激活的字线; 根据银行信息，从活动字线向银行读/写存储内容。

公开(公告)号：US20080068913A1

公开(公告)日：2008-03-20

申请号：US11856621

申请日：2007-09-17

申请人： Christian Sichert ,  Paul Wallner

发明人： Christian Sichert ,  Paul Wallner

IPC分类号： G11C7/00

CPC分类号： G11C11/406

摘要： A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.

摘要翻译： 刷新存储器装置的存储单元的内容的方法包括经由存储器装置的接口或存储器装置的内部控制装置选择性地控制存储器装置的刷新装置，以刷新存储器装置的内容。

公开(公告)号：US07334150B2

公开(公告)日：2008-02-19

申请号：US11002148

申请日：2004-12-03

申请人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G06F1/04

CPC分类号： G11C5/04 ,  G11C5/063

摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

公开(公告)号：US20060104132A1

公开(公告)日：2006-05-18

申请号：US10986767

申请日：2004-11-15

申请人： Hermann Ruckerbauer ,  Dominique Savignac ,  Christian Sichert ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Dominique Savignac ,  Christian Sichert ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/1018

摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.

摘要翻译： 用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串 具体的突发长度。 该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

公开(公告)号：US06188273B1

公开(公告)日：2001-02-13

申请号：US09408476

申请日：1999-09-28

申请人： Rainer Bartenschlager ,  Christian Sichert ,  Zoltan Manyoki

发明人： Rainer Bartenschlager ,  Christian Sichert ,  Zoltan Manyoki

IPC分类号： H01L2500

CPC分类号： H03K19/1731

摘要： An integrated circuit has a first voltage generator, which is connected via a first switching element to a contact-making point for external contact making with the circuit. In addition, it has a first digital control device, via which the contact-making point is connected to a control input of the first switching element. In this case, the first control device switches the first switching element on or turns the latter off by a first digital control signal, the level of which is dependent on the potential of the contact-making point. Furthermore, the contact-making point is connected to the input of a second digital control device, which supplies a digital operating mode signal at its output, the level of which operating mode signal is dependent on the potential of the contact-making point.

摘要翻译： 集成电路具有第一电压发生器，其经由第一开关元件连接到用于与电路进行外部接触的接触点。 此外，它具有第一数字控制装置，通过该第一数字控制装置将接触点连接到第一开关元件的控制输入端。 在这种情况下，第一控制装置将第一开关元件接通或使其断开第一数字控制信号，该第一数字控制信号的电平取决于接触点的电位。 此外，接触点连接到第二数字控制装置的输入，该第二数字控制装置在其输出处提供数字操作模式信号，其操作模式信号的电平取决于接触点的电位。

公开(公告)号：US07663965B2

公开(公告)日：2010-02-16

申请号：US11761004

申请日：2007-06-11

申请人： Falk Roewer ,  Florian Schnabel ,  Christian Sichert

发明人： Falk Roewer ,  Florian Schnabel ,  Christian Sichert

IPC分类号： G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22

摘要： An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.

摘要翻译： 具有时钟控制存储器访问的集成电路存储器包括至少一个到输入/输出数据的数据连接，存储单元阵列，包括用于存储数据的存储器单元，用于产生时钟信号的时钟发生器电路，存储数据的存储电路， 控制电路，用于控制存储器电路中的数据存储并控制来自存储器电路的数据的输出。 存储器电路连接到存储单元阵列和至少一个数据连接。 在对存储器单元的读取访问期间，从存储单元阵列提供给存储器电路的第一和第二数据在时钟信号的第一和第二边沿缓冲存储在存储器电路中。 第一和第二数据从存储器电路输出并在时钟信号的第三和第四边缘提供给至少一个数据连接。

公开(公告)号：US07428689B2

公开(公告)日：2008-09-23

申请号：US11217081

申请日：2005-08-30

申请人： Paul Wallner ,  Dominique Savignac ,  Christian Sichert ,  Thomas Hein

发明人： Paul Wallner ,  Dominique Savignac ,  Christian Sichert ,  Thomas Hein

IPC分类号： G06F11/10

CPC分类号： G06F13/4243 ,  G06F11/1052

摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

摘要翻译： 提出了一种使用数据协议将数据传输到数据存储器中的方法。 数据存储器是纠错码（ECC）存储器或非纠错码存储器。 数据协议具有不同的帧。 当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。 该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

公开(公告)号：US20080181044A1

公开(公告)日：2008-07-31

申请号：US11700399

申请日：2007-01-31

申请人： Christian Sichert ,  Rainer Bartenschlager ,  Jens Polney

发明人： Christian Sichert ,  Rainer Bartenschlager ,  Jens Polney

IPC分类号： H03K3/00 ,  G11C8/00

CPC分类号： G06F13/4243 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096

摘要： A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.

摘要翻译： 总线结构包括多个驱动器电路，每个驱动电路包括用于第一信号的输入端和用于输出信号的端子，其中每个驱动电路能够在接收到第一信号时在端子处提供输出信号，并联 总线包括在接收端处的多个输出信号线，可连接到目标分量，每个信号线至少从多个驱动器电路中的不同驱动电路的接收端延伸到终端，使得长度 接收端与各个驱动电路之间的输出信号线在多个驱动电路之间以连接顺序减小，以及以连接顺序耦合到驱动器电路的每个输入的信号线。

公开(公告)号：US07391657B2

公开(公告)日：2008-06-24

申请号：US11751984

申请日：2007-05-22

申请人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

发明人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C11/4096

摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。

公开(公告)号：US20070291554A1

公开(公告)日：2007-12-20

申请号：US11761004

申请日：2007-06-11

申请人： Falk Roewer ,  Florian Schnabel ,  Christian Sichert

发明人： Falk Roewer ,  Florian Schnabel ,  Christian Sichert

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22

摘要： An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.

摘要翻译： 具有时钟控制存储器访问的集成电路存储器包括至少一个到输入/输出数据的数据连接，存储单元阵列，包括用于存储数据的存储器单元，用于产生时钟信号的时钟发生器电路，存储数据的存储电路， 控制电路，用于控制存储器电路中的数据存储并控制来自存储器电路的数据的输出。 存储器电路连接到存储单元阵列和至少一个数据连接。 在对存储器单元的读取访问期间，从存储单元阵列提供给存储器电路的第一和第二数据在时钟信号的第一和第二边沿缓冲存储在存储器电路中。 第一和第二数据从存储器电路输出并在时钟信号的第三和第四边缘提供给至少一个数据连接。