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公开(公告)号：US06646323B2
公开(公告)日：2003-11-11
申请号：US09849730
申请日：2001-05-04
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor. The resulting capacitor has a relatively large effective electrode surface area (which is a function of the depth of the via) for a given lateral dimension.
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2.发明授权Method and electronic device for a simplified integration of high precision thinfilm resistors 有权方法和电子设备，用于简化高精度薄膜电阻的集成公开(公告)号：US08470683B2
公开(公告)日：2013-06-25
申请号：US13032426
申请日：2011-02-22
CPC分类号： H01L28/20 , H01L21/76816 , H01L23/5228 , H01L27/016 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.
摘要翻译： 本发明涉及一种制造集成电路的方法。 沉积用作薄膜电阻器（TFR）的材料的电阻层。 第一电绝缘层沉积在TFR的电阻层上。 沉积导电材料的导电层。 没有导电层而没有区域与TFR的电阻层重叠。 第二电绝缘层沉积在导电层的顶部上。 通过第二绝缘层蚀刻第一VIA开口，没有导电层的区域与导电层相邻并且通过第一绝缘层直到TFR的电阻层。 在第一VIA开口中沉积导电材料，以电连接TFR的导电层和电阻层。
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公开(公告)号：US20080265368A1
公开(公告)日：2008-10-30
申请号：US11740467
申请日：2007-04-26
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).
摘要翻译： 集成堆叠电容器包括多晶硅化物（poly）的第一电容器膜（46），夹在第一电容器膜（46）和第二电容器膜（48）之间的第二电容器膜（48）和第一电介质（26）。 提供第二电介质（34）和第三电容膜（50）。 第二电介质（34）夹在第二电容器膜（48）和第三电容器膜（50）之间。 一种用于制造集成叠层电容器的方法包括以下步骤：施加多晶硅层（20）以形成第一电容器膜（46）; 施加第一电介质（26）; 施加第一金属化层（28）以形成第二电容器膜（48）; 施加第二电介质（34）; 以及施加第二金属化层（34）以形成所述第三电容器膜（50）。
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公开(公告)号：US07227241B2
公开(公告)日：2007-06-05
申请号：US10850797
申请日：2004-05-20
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).
摘要翻译： 集成堆叠电容器包括多晶硅化物（poly）的第一电容器膜（46），夹在第一电容器膜（46）和第二电容器膜（48）之间的第二电容器膜（48）和第一电介质（26）。 提供第二电介质（34）和第三电容膜（50）。 第二电介质（34）夹在第二电容器膜（48）和第三电容器膜（50）之间。 一种用于制造集成叠层电容器的方法包括以下步骤：施加多晶硅层（20）以形成第一电容器膜（46）; 施加第一电介质（26）; 施加第一金属化层（28）以形成第二电容器膜（48）; 施加第二电介质（34）; 以及施加第二金属化层（34）以形成所述第三电容器膜（50）。
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公开(公告)号：US07736986B2
公开(公告)日：2010-06-15
申请号：US11740467
申请日：2007-04-26
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (44) to form the third capacitor film (50).
摘要翻译： 集成堆叠电容器包括多晶硅化物的第一电容器膜（46），夹在第一电容器膜（46）和第二电容器膜（48）之间的第二电容器膜（48）和第一电介质（26）。 提供第二电介质（34）和第三电容膜（50）。 第二电介质（34）夹在第二电容器膜（48）和第三电容器膜（50）之间。 一种用于制造集成叠层电容器的方法包括以下步骤：施加多晶硅层（20）以形成第一电容器膜（46）; 施加第一电介质（26）; 施加第一金属化层（28）以形成第二电容器膜（48）; 施加第二电介质（34）; 以及施加第二金属化层（44）以形成所述第三电容器膜（50）。
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公开(公告)号：US20100136764A1
公开(公告)日：2010-06-03
申请号：US12624442
申请日：2009-11-24
IPC分类号： H01L21/02
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.
摘要翻译： 一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层 对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。
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公开(公告)号：US07164186B2
公开(公告)日：2007-01-16
申请号：US10939221
申请日：2004-09-10
IPC分类号： H01L29/70
CPC分类号： H01L29/66272 , H01L29/41708
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
摘要翻译： 半导体器件的制造方法包括形成半导体衬底的掩埋层。 在掩埋层的至少一部分附近形成有源区。 在掩埋层的至少一部分附近形成第一隔离结构。 在活性区域的至少一部分附近形成第二隔离结构。 在活性区域的至少一部分附近形成基底层。 在基底层的至少一部分附近形成电介质层，然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。 发射极结构形成在发射极接触位置。 形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。 沉降片接触区域具有第一深度。 该方法还可以包括形成栅极结构。 形成栅极结构包括蚀刻沉降片接触区域，从而将沉降片接触区域的第一深度增加到第二深度。
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8.发明授权公开(公告)号：US06774455B2
公开(公告)日：2004-08-10
申请号：US10262206
申请日：2002-09-30
申请人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
发明人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
IPC分类号： H01L29737
CPC分类号： H01L29/66265 , H01L29/41708 , H01L29/66272 , H01L29/7317 , H01L29/732
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
摘要翻译： 半导体器件的制造方法包括形成半导体衬底的掩埋层。 在掩埋层的至少一部分附近形成有源区。 移除活性区域的至少一部分以形成浅沟槽开口。 在浅沟槽开口内至少部分地在有源区域附近形成电介质层。 去除介电层的至少一部分以形成集电极接触区域。 集电极触点可以在集电极接触区域形成。 集电极触点可操作以电接触埋层。
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9.发明申请Method and Electronic Device for a Simplified Integration of High Precision Thinfilm Resistors 有权用于简化高精度薄膜电阻器集成的方法和电子设备公开(公告)号：US20110204482A1
公开(公告)日：2011-08-25
申请号：US13032426
申请日：2011-02-22
CPC分类号： H01L28/20 , H01L21/76816 , H01L23/5228 , H01L27/016 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.
摘要翻译： 本发明涉及一种制造集成电路的方法。 沉积用作薄膜电阻器（TFR）的材料的电阻层。 第一电绝缘层沉积在TFR的电阻层上。 沉积导电材料的导电层。 没有导电层而没有区域与TFR的电阻层重叠。 第二电绝缘层沉积在导电层的顶部上。 通过第二绝缘层蚀刻第一VIA开口，没有导电层的区域与导电层相邻并且通过第一绝缘层直到TFR的电阻层。 在第一VIA开口中沉积导电材料，以电连接TFR的导电层和电阻层。
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公开(公告)号：US20070069269A1
公开(公告)日：2007-03-29
申请号：US11549248
申请日：2006-10-13
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0805
摘要： The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
摘要翻译： 本发明涉及一种堆叠式电容器（10），包括硅基板（16），布置在基板（16）上方的多晶硅中心板（32），下栅极氧化物电介质（26） 板（16）和中心板（32），由中心板（32）上方布置的金属导体制成的盖板（36）和布置在中心板（32）和 盖板（36）。 盖板（36）和基板（16）彼此电连接并一起形成第一电容器电极。 中心板（32）形成第二电容器电极。 本发明还涉及具有这种堆叠电容器的集成电路，以及作为CMOS工艺的一部分的用于制造堆叠电容器的方法。
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