摘要:
The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
摘要:
A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.
摘要:
The invention relates to a laminated layer structure that includes a substrate and a stack of a plurality of layers of a material that includes at least two compounds A and B, wherein compound A has a crystalline structure being sufficient to allow a homo- or heteroepitaxial growth of compound A on the substrate, and wherein at least a part of the layers of the stack have a gradient composition AxB(1-xg), with x being a composition parameter within the range of 0 and 1 and with the composition parameter (1-xg) increasing gradually, in particular linearly, over the thickness of the corresponding layer. In order to improve the quality of the laminated layer structure with respect to the surface roughness and dislocation density, the composition parameter at the interface between the layer in the stack with the gradient composition and the subsequent layer in the stack is chosen to be smaller than the composition parameter (1-xg) of the layer with a gradient composition. The invention also relates to a method to fabricate such a laminated layer structure.
摘要翻译:本发明涉及层压层结构,其包括基材和包含至少两种化合物A和B的多层材料的叠层,其中化合物A具有足以允许同质或异质外延生长的晶体结构 的化合物A,并且其中堆叠的至少一部分层具有梯度组合物A x B(1-x g),其中x是 组成参数在0和1的范围内,并且组成参数(1-x<>>)在相应层的厚度上逐渐增加,特别是线性增加。 为了提高相对于表面粗糙度和位错密度的叠层结构的质量,将层叠层与梯度组成之间的界面处的组成参数和堆叠中的后续层选择为小于 具有梯度组成的层的组成参数(1-x g g)。 本发明还涉及制造这种叠层结构的方法。
摘要:
Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.
摘要:
Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.
摘要:
The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.15 nm RMS in a 2×2 μm2 or a 10×10 μm2 scan, and depositing epitaxially a silicon layer with (110) orientation on the basic silicon substrate at a pressure between 40 Torr to 120 Torr, preferably 80 Torr and at a temperature between about 1000° C. and about 1200° C. and using trichlorosilane or dichlorosilane as silicon precursor gas.
摘要:
A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate
摘要:
A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate
摘要:
A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure possess a lower surface roughness than other heterostructures. In the heterostructure, the ungraded layers are strained layers that comprise at least one strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between the first and the second lattice parameter.
摘要:
The invention relates to an electronic device for radiofrequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/mK and a superficial layer having a thickness of at least 5 μm, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/mK. The invention also relates to two processes for manufacturing such a device.