SEMICONDUCTOR HETEROSTRUCTURE AND METHOD FOR FORMING SAME
    1.
    发明申请
    SEMICONDUCTOR HETEROSTRUCTURE AND METHOD FOR FORMING SAME 有权
    半导体结构及其形成方法

    公开(公告)号:US20100264463A1

    公开(公告)日:2010-10-21

    申请号:US12827135

    申请日:2010-06-30

    IPC分类号: H01L29/12

    摘要: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

    摘要翻译: 本发明涉及一种用于通过向第一面内晶格参数a1提供衬底来形成半导体异质结构的方法,为缓冲层提供第二面内晶格参数a2并在缓冲层上提供顶层。 为了改善半导体异质结构的表面粗糙度,在缓冲层和顶层之间提供附加层,其中附加层具有在第一和第二晶格参数之间的第三面内晶格参数a3 。

    Method of manufacturing a semiconductor heterostructure
    2.
    发明授权
    Method of manufacturing a semiconductor heterostructure 有权
    半导体异质结构的制造方法

    公开(公告)号:US07459374B2

    公开(公告)日:2008-12-02

    申请号:US11674392

    申请日:2007-02-13

    IPC分类号: H01L21/00 H01L21/302

    摘要: A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.

    摘要翻译: 一种半导体异质结构的制造方法,首先制造具有第一面内晶格参数的第一衬底的施主晶片,具有第二面内晶格参数的空间渐变缓冲层,以及半导体材料的应变平滑化层, 具有第一和第二格子参数之间的值的第三平面晶格参数。 顶层在未分级层上形成具有顶表面的半导体材料的顶层,任选具有位于顶表面上的表层,并具有等于或小于10纳米的厚度。 接下来,其上具有绝缘体层的第二衬底的处理晶片与施主晶片接合,使得(a)把手晶片的绝缘体层直接接合到施主晶片顶层的顶表面上, 或者(b)把手晶片的绝缘体层结合到表面层上。

    Laminated layer structure and method for forming the same
    3.
    发明申请
    Laminated layer structure and method for forming the same 有权
    层压结构及其形成方法

    公开(公告)号:US20060211230A1

    公开(公告)日:2006-09-21

    申请号:US11146572

    申请日:2005-06-06

    申请人: Christophe Figuet

    发明人: Christophe Figuet

    摘要: The invention relates to a laminated layer structure that includes a substrate and a stack of a plurality of layers of a material that includes at least two compounds A and B, wherein compound A has a crystalline structure being sufficient to allow a homo- or heteroepitaxial growth of compound A on the substrate, and wherein at least a part of the layers of the stack have a gradient composition AxB(1-xg), with x being a composition parameter within the range of 0 and 1 and with the composition parameter (1-xg) increasing gradually, in particular linearly, over the thickness of the corresponding layer. In order to improve the quality of the laminated layer structure with respect to the surface roughness and dislocation density, the composition parameter at the interface between the layer in the stack with the gradient composition and the subsequent layer in the stack is chosen to be smaller than the composition parameter (1-xg) of the layer with a gradient composition. The invention also relates to a method to fabricate such a laminated layer structure.

    摘要翻译: 本发明涉及层压层结构,其包括基材和包含至少两种化合物A和B的多层材料的叠层,其中化合物A具有足以允许同质或异质外延生长的晶体结构 的化合物A,并且其中堆叠的至少一部分层具有梯度组合物A x B(1-x g),其中x是 组成参数在0和1的范围内,并且组成参数(1-x<>>)在相应层的厚度上逐渐增加,特别是线性增加。 为了提高相对于表面粗糙度和位错密度的叠层结构的质量,将层叠层与梯度组成之间的界面处的组成参数和堆叠中的后续层选择为小于 具有梯度组成的层的组成参数(1-x g g)。 本发明还涉及制造这种叠层结构的方法。

    DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES
    4.
    发明申请
    DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES 有权
    用于形成III / V半导体材料的沉积方法及相关结构

    公开(公告)号:US20130049012A1

    公开(公告)日:2013-02-28

    申请号:US13659521

    申请日:2012-10-24

    IPC分类号: H01L29/205

    摘要: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

    摘要翻译: 形成三元III族氮化物材料的方法包括在室中的衬底上的外延生长三元III族氮化物材料。 外延生长包括在室内提供前体气体混合物,其包括氮气前体的分压与腔室中一种或多种III族前体的分压的相对高的比例。 至少部分地由于相对高的比例,可以将三元III族氮化物材料层生长到具有小的V凹坑缺陷的高最终厚度。 使用这种方法制造包括这种三元III族氮化物材料层的半导体结构。

    (110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES COMPRISING SAID (110) ORIENTED SILICON SUBSTRATE
    6.
    发明申请
    (110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES COMPRISING SAID (110) ORIENTED SILICON SUBSTRATE 有权
    (110)面向硅的衬底和包含固体(110)的硅衬底的衬底的粘合对

    公开(公告)号:US20100038756A1

    公开(公告)日:2010-02-18

    申请号:US12450295

    申请日:2008-02-26

    IPC分类号: H01L29/04 H01L21/18

    摘要: The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.15 nm RMS in a 2×2 μm2 or a 10×10 μm2 scan, and depositing epitaxially a silicon layer with (110) orientation on the basic silicon substrate at a pressure between 40 Torr to 120 Torr, preferably 80 Torr and at a temperature between about 1000° C. and about 1200° C. and using trichlorosilane or dichlorosilane as silicon precursor gas.

    摘要翻译: 本发明涉及一种制造(110)定向硅衬底的方法以及一种制造包括这种(110)定向硅衬底的粘结对衬底对的方法。 本发明还涉及具有(110)取向的硅衬底和包括具有(100)取向的第一硅衬底和具有(110)取向的第二硅衬底的键合的一对硅衬底。 本发明的目的是提供高效率的上述类型的方法和基底,其中所形成的(110)基底至少具有接近和在其表面上几乎没有缺陷。 本发明的目的是通过制造具有(110)取向的硅衬底的方法和通过制造粘合的一对硅衬底的方法来解决的,包括以下步骤:提供具有(110)取向的碱性硅衬底,所述碱性硅衬底具有 在2×2μm2或10×10μm2扫描中的粗糙度等于或小于0.15nm RMS,并且在40Torr至120Torr之间的压力下,以(110)取向外延地在碱性硅衬底上沉积硅层, 优选为80托,温度为约1000℃至约1200℃,并使用三氯硅烷或二氯硅烷作为硅前体气体。

    STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES
    7.
    发明申请
    STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES 有权
    半导体缓冲器结构中的应变层

    公开(公告)号:US20100006893A1

    公开(公告)日:2010-01-14

    申请号:US12562029

    申请日:2009-09-17

    IPC分类号: H01L29/12

    摘要: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate

    摘要翻译: 包括衬底的半导体工件,包括形成在衬底上的渐变部分的松弛缓冲层以及缓和缓冲层的渐变部分内的至少一个应变过渡层及其制造方法。 至少一个应变过渡层由于松弛缓冲层相对于衬底的CTE收缩的差热膨胀系数(CTE)收缩而减少了工件弓的数量

    Strained layers within semiconductor buffer structures
    8.
    发明授权
    Strained layers within semiconductor buffer structures 有权
    半导体缓冲结构内的应变层

    公开(公告)号:US07608526B2

    公开(公告)日:2009-10-27

    申请号:US11491616

    申请日:2006-07-24

    IPC分类号: H01L21/20

    摘要: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate

    摘要翻译: 包括衬底的半导体工件,包括形成在衬底上的渐变部分的松弛缓冲层以及缓和缓冲层的渐变部分内的至少一个应变过渡层及其制造方法。 至少一个应变过渡层由于松弛缓冲层相对于衬底的CTE收缩的差热膨胀系数(CTE)收缩而减少了工件弓的数量

    SEMICONDUCTOR HETEROSTRUCTURE
    9.
    发明申请
    SEMICONDUCTOR HETEROSTRUCTURE 有权
    半导体结构

    公开(公告)号:US20080142844A1

    公开(公告)日:2008-06-19

    申请号:US11672663

    申请日:2007-02-08

    IPC分类号: H01L29/04

    摘要: A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure possess a lower surface roughness than other heterostructures. In the heterostructure, the ungraded layers are strained layers that comprise at least one strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between the first and the second lattice parameter.

    摘要翻译: 一种半导体异质结构,其包括具有第一面内晶格参数的支撑衬底,形成在所述支撑衬底上并且处于松弛状态的顶部具有第二面内晶格参数的缓冲结构,以及未层压层的多层堆叠 形成在缓冲结构上。 该半导体异质结构具有比其它异质结构更低的表面粗糙度。 在异质结构中,未分级层是包含处于松弛状态的半导体材料的至少一个应变平滑层的应变层,其具有在第一和第二晶格参数之间的值的第三平面晶格参数。