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1.发明申请公开(公告)号：US20170017580A1
公开(公告)日：2017-01-19
申请号：US15281383
申请日：2016-09-30
IPC分类号： G06F12/122 , G06F3/06
CPC分类号： G06F12/122 , G06F3/06 , G06F3/061 , G06F3/0644 , G06F3/0647 , G06F3/0673 , G06F12/0893 , G06F2212/1016 , G11C7/1072
摘要： An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.
摘要翻译： 描述了用于实现异构存储器子系统的装置和方法。 例如，处理器的一个实施例包括：存储器映射逻辑，用于将系统存储器空间细分成多个存储器块，并且跨越第一存储器和第二存储器映射存储器块，第一存储器具有第一组存储器访问 特性和第二存储器具有不同于第一组存储器访问特性的第二组存储器存取特性; 以及动态重映射逻辑，用于至少部分地基于访问存储器块的检测频率来交换第一和第二存储器之间的存储器块。
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公开(公告)号：US08719502B2
公开(公告)日：2014-05-06
申请号：US13436758
申请日：2012-03-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F2212/1032 , G06F2212/604 , Y02D10/13
摘要： A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.
摘要翻译： 用于操作包括鲁棒单元和标准单元的高速缓存的方法可以包括接收要写入高速缓存的数据，确定数据类型是未修改数据还是修改数据，以及将数据写入鲁棒单元或标准单元 作为数据类型的函数。 处理器包括核心，其包括包括鲁棒单元和用于接收数据的标准单元的高速缓存，其中根据是否将数据类型确定为未修改数据或修改数据，将数据写入鲁棒单元或标准单元 。
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公开(公告)号：US20130326263A1
公开(公告)日：2013-12-05
申请号：US13485474
申请日：2012-05-31
IPC分类号： G06F11/20
CPC分类号： G06F11/27 , G06F11/1048 , G06F11/2205
摘要： Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.
摘要翻译： 实施例包括动态可分配的存储器错误缓解的方法和系统。 在一个实施例中，系统将错误缓解机制应用于多组存储器单元中的一组，其中在第二组存储器单元的错误测试期间，一组正在使用。 系统停用并测试第二组存储器单元的错误。 响应于检测到第二组的存储器单元中的错误，系统向具有错误的第二组的存储器单元应用用于主动使用的错误减轻机制。 然后，该系统激活第二组存储器单元，其中将误差减轻机制应用于具有该错误的第二组的存储器单元。
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公开(公告)号：US06931490B2
公开(公告)日：2005-08-16
申请号：US09738088
申请日：2000-12-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： Set address correlation correlates between addresses belonging to a common address set. Addresses are grouped into address sets and correlations are created between addresses by set. The correlations are used to predict future addresses based on current addresses.
摘要翻译： 设置地址相关性在属于公共地址集的地址之间相关。 地址被分组成地址集，并且通过集合在地址之间创建相关性。 相关性用于根据当前地址预测未来地址。
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公开(公告)号：US06785797B2
公开(公告)日：2004-08-31
申请号：US09741371
申请日：2000-12-19
IPC分类号： G06F1206
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.
摘要翻译： 用于寻址预测在高性能计算系统中有用的装置和方法。 本发明提供了新的相关预测表。 在一个实施例中，本发明的相关预测表包含输入到相关表中的每个后续值的输入密钥。 在第二实施例中，本发明的相关预测表利用输入的键和输入的后继值的地址偏移。
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公开(公告)号：US06662273B1
公开(公告)日：2003-12-09
申请号：US09676522
申请日：2000-09-29
IPC分类号： G06F1200
CPC分类号： G06F12/122 , G06F12/0862 , G06F12/0888 , G06F12/121
摘要： The critical cache tracks a critical score for each cache line in the critical cache. On cache hits, the critical score of the hit cache line is incremented by an instance score assigned to the data request. On cache misses, data may be retrieved from main memory without allocating a cache line into the critical cache, in which case the instance score is subtracted from the critical scores of all cache lines in the cache. Alternatively on a cache miss, the cache line with the smallest critical score is removed from the cache. The smallest critical score is then subtracted from each cache line in the critical cache. A new cache line is allocated that satisfies the data request, and the new cache line is given the instance score of the data request as a critical score.
摘要翻译： 关键缓存跟踪关键缓存中每个缓存行的关键分数。 在缓存命中时，命中缓存行的临界得分增加了分配给数据请求的实例得分。 在缓存未命中时，可以从主存储器检索数据，而不将高速缓存行分配到关键高速缓存中，在这种情况下，从缓存中的所有高速缓存行的关键分数中减去实例分数。 或者在缓存未命中时，从缓存中移除具有最小关键分数的高速缓存行。 然后从关键缓存中的每个缓存行中减去最小的关键分数。 分配满足数据请求的新的高速缓存行，并且将新的高速缓存行作为关键分数给出数据请求的实例分数。
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公开(公告)号：US09378021B2
公开(公告)日：2016-06-28
申请号：US14181032
申请日：2014-02-14
申请人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
发明人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/3808 , G06F9/383 , G06F2212/6026
摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.
摘要翻译： 处理器包括高速缓存，根据预取器算法选择信息的预取器模块以及预取器算法选择模块。 预取器算法选择模块包括选择候选预取器算法的逻辑，当由预取器模块执行时，确定并存储候选预取器算法的预测存储器访问的存储器地址，确定在存储器操作期间访问的高速缓存行，并且评估所确定的高速缓存行是否匹配 存储的存储器地址。 预取器算法选择模块还包括用于调整候选预取器算法的准确率的逻辑，将精度比与阈值精度比进行比较，并且确定是否将第一候选预取器算法应用于预取器模块。
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公开(公告)号：US09189014B2
公开(公告)日：2015-11-17
申请号：US13664153
申请日：2012-10-30
申请人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
发明人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC分类号： G06F11/07 , G06F1/08 , G06F1/10 , H03K3/037 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译： 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。
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9.发明申请公开(公告)号：US20150095918A1
公开(公告)日：2015-04-02
申请号：US14040142
申请日：2013-09-27
CPC分类号： G06F12/0811 , G06F9/5061 , G06F12/0842 , G06F2209/5012 , Y02D10/13 , Y02D10/22 , Y02D10/36
摘要： Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.
摘要翻译： 有效利用可重构处理器核心的系统和方法。 示例性处理系统包括例如包括多个禁止位的控制寄存器，每个禁止位指示是否允许相应的处理器核与其他处理器内核合并; 以及动态核心重新分配逻辑，用于临时合并第一处理器核心和第二处理器核心，以响应于确定在第二处理器核心上执行的第二线程在量化之前已经完成执行，以加速在第一处理器核心上执行的第一线程的执行 与第二线程相关联并且确定禁止比特指示第一和第二核可以被合并。
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公开(公告)号：US20110154002A1
公开(公告)日：2011-06-23
申请号：US12640707
申请日：2009-12-17
申请人： Wei Liu , Youfeng Wu , Christopher B. Wilkerson , Herbert H. Hum
发明人： Wei Liu , Youfeng Wu , Christopher B. Wilkerson , Herbert H. Hum
IPC分类号： G06F9/38
CPC分类号： G06F12/0888 , G06F8/4442 , G06F9/30043 , G06F9/3826 , G06F9/383 , Y02D10/13
摘要： Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.
摘要翻译： 本发明的各种实施例涉及用于功率和时间有效的负载处理的方法和装置。 编译器可以识别生产者负载，消费者重用负载，消费者转发负载以及生产者/消费者混合负载。 基于该识别，可以将负载的性能有效地指向负载值缓冲器，存储缓冲器，数据高速缓存或其他位置。 因此，通过从负载值缓冲区和存储缓冲区直接加载，从而降低对高速缓存的访问，从而有效地处理负载。
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