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    VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION
    2.
    发明申请
    VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION 有权
    具有主要载体累积层的垂直双极晶体管，作为用于SOI BiCMOS的半导体器件，具有减少的基底氧化物厚度用于低基板偏压运行

    公开(公告)号：US20080261371A1

    公开(公告)日：2008-10-23

    申请号：US12144998

    申请日：2008-06-24

    申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiging Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiging Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

    摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

    摘要翻译： 本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。 还提供了背栅CMOS装置。

    METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES
    3.
    发明申请
    METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效
    用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件

    公开(公告)号：US20090189242A1

    公开(公告)日：2009-07-30

    申请号：US12020887

    申请日：2008-01-28

    申请人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

    发明人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

    IPC分类号： H01L29/00 ,  H01L21/762

    CPC分类号： H01L29/045 ,  H01L21/76224

    摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

    摘要翻译： 公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向 和具有第二结晶取向的体区。 使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个 材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。 可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

    ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF
    5.
    发明申请
    ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF 审中-公开
    具有用于低基板偏移操作的薄层氧化物（盒）上的反相收集器的超薄SOI垂直双极晶体管及其方法

    公开(公告)号：US20080132025A1

    公开(公告)日：2008-06-05

    申请号：US11877305

    申请日：2007-10-23

    申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7317

    摘要： The present invention provides a “collector-less” silcon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BIJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

    摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SIL）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反转层。这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BIJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

    CMOS circuits including a passive element having a low end resistance
    6.
    发明授权
    CMOS circuits including a passive element having a low end resistance 有权
    CMOS电路包括具有低端电阻的无源元件

    公开(公告)号：US07361959B2

    公开(公告)日：2008-04-22

    申请号：US11164515

    申请日：2005-11-28

    申请人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

    发明人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0629 ,  H01L21/26506 ,  H01L28/20 ,  H01L28/40 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.

    摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。 更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆 微量元素 这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件 基本上没有前非晶化植入物。

    Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
    8.
    发明授权
    Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation 失效
    具有绝大多数载流子积累层的垂直双极晶体管作为用于SOI BiCMOS的子集电极，具有降低的掩埋氧化物厚度以用于低衬底偏置操作

    公开(公告)号：US07115965B2

    公开(公告)日：2006-10-03

    申请号：US10931855

    申请日：2004-09-01

    申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    IPC分类号： H01L29/70

    CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

    摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

    摘要翻译： 本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。 还提供了背栅CMOS装置。

    Filling narrow openings using ion beam etch
    9.
    发明授权
    Filling narrow openings using ion beam etch 有权
    使用离子束蚀刻填充窄孔

    公开(公告)号：US08497212B2

    公开(公告)日：2013-07-30

    申请号：US13036113

    申请日：2011-02-28

    申请人： Katherina E. Babich ,  Alessandro C. Callegari ,  Christopher D. Sheraw ,  Eugene J. O'Sullivan

    发明人： Katherina E. Babich ,  Alessandro C. Callegari ,  Christopher D. Sheraw ,  Eugene J. O'Sullivan

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.

    摘要翻译： 通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中可以使用多层金属填充物来填充形成在层间电介质层中的窄开口。 本文公开的一种说明性方法包括在半导体衬底上形成的半导体器件的电介质材料层中形成开口，该开口具有侧壁和底表面。 该方法还包括通过在开口内形成第一层并且至少在开口的侧壁和底表面上方形成在半导体器件上方形成第一填充材料层。 此外，该方法包括执行第一成角度蚀刻工艺，以通过至少部分地去除开口的入口附近的第一层的第一部分，而不去除第二填充材料的第二层，从而从半导体器件的上方至少部分地去除第一填充材料层 所述第一层的部分靠近所述开口的底部，并且通过在所述开口内部和所述第一层上方形成所述第二层，在所述半导体器件上方形成第二填充材料层。

    Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof
    10.
    发明授权
    Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof 失效
    具有用于低衬底偏置操作的薄埋氧化物（BOX）上的反向集电极的超薄SOI垂直双极晶体管及其方法

    公开(公告)号：US07763518B2

    公开(公告)日：2010-07-27

    申请号：US12099437

    申请日：2008-04-08

    申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7317

    摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

    摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。