公开(公告)号：US20050060511A1

公开(公告)日：2005-03-17

申请号：US10662734

申请日：2003-09-15

申请人： Christopher Ruemmler ,  Fani Pavlova

发明人： Christopher Ruemmler ,  Fani Pavlova

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/023 ,  G06F12/145 ,  Y10S707/99953 ,  Y10S707/99956

摘要： One embodiment disclosed relates to a computer system. The computer system includes a microprocessor, an operating system, and a memory system. The microprocessor includes a register stack and a register stack engine (RSE), and the operating system includes a kernel. The memory system is configured to have a single memory page that includes both a kernel stack and an RSE stack. The memory system may be further configured such that the kernel stack and the RSE stack grow in opposite directions and such that a uarea data structure is located between those two stacks.

摘要翻译： 所公开的一个实施例涉及一种计算机系统。 计算机系统包括微处理器，操作系统和存储器系统。 微处理器包括寄存器堆栈和寄存器堆栈引擎（RSE），并且操作系统包括内核。 内存系统配置为具有包含内核堆栈和RSE堆栈的单个内存页面。 可以进一步配置存储器系统，使得内核堆栈和RSE堆栈以相反的方向生长，并且使得uarea数据结构位于这两个堆栈之间。

公开(公告)号：US20060069833A1

公开(公告)日：2006-03-30

申请号：US10950994

申请日：2004-09-27

申请人： Christopher Ruemmler ,  Matthew Fischer

发明人： Christopher Ruemmler ,  Matthew Fischer

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performing interrupt handling of the working interrupt vectors using an interrupt handling arrangement until the working list is empty. The interrupt handling process permits a first incoming interrupt vector that is received by the pending interrupt list after the batch reading to temporarily interrupt the performing interrupt handling of the working interrupt vectors and to be handled on a priority basis by the interrupt handling arrangement if a priority level of the first incoming interrupt vector is higher than a priority level of a first working interrupt vector being currently handled by the interrupt handling arrangement.

摘要翻译： 公开了一种用于处理未决中断列表的未决中断向量的计算机实现的方法。 该方法包括将一组待处理的中断向量批量读取到工作中断向量的工作列表中。 该方法还包括使用中断处理装置执行工作中断向量的中断处理，直到工作列表为空。 中断处理过程允许在批量读取之后由等待中断列表接收到的第一输入中断向量，以暂时中断对工作中断向量的执行中断处理，并且如果优先级通过中断处理装置在优先级处理 第一输入中断向量的电平高于当前由中断处理装置处理的第一工作中断向量的优先级。

公开(公告)号：US20050066096A1

公开(公告)日：2005-03-24

申请号：US10670026

申请日：2003-09-24

申请人： Christopher Ruemmler ,  Jonathan Ross

发明人： Christopher Ruemmler ,  Jonathan Ross

IPC分类号： G06F12/14

CPC分类号： G06F9/30101 ,  G06F9/30116 ,  G06F9/3863

摘要： One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.

摘要翻译： 公开的一个实施例涉及一种减少对微处理器内的本地可编程中断控制器单元的任务优先级寄存器（TPR）的访问等待时间的方法。 接收到向TPR写入中断屏蔽值的命令，并将中断屏蔽值写入TPR。 此外，中断屏蔽值也被写入TPR的卷影副本。 每次写入TPR时都会写入影子副本。 所公开的另一实施例涉及一种减少读取IPF型微处理器的TPR的等待时间的方法。 当接收到从TPR读取中断屏蔽值的命令时，中断屏蔽值将从存储器位置的卷影副本中读取，而不是从任务优先级寄存器本身读取。