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    Charge Pump System
    1.
    发明申请
    Charge Pump System 有权
    电荷泵系统

    公开(公告)号：US20130285737A1

    公开(公告)日：2013-10-31

    申请号：US13460112

    申请日：2012-04-30

    Applicant: Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

    Inventor： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

    IPC: G05F3/02

    CPC classification number: H02M3/07

    Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

    Abstract translation: 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

    DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF
    2.
    发明申请
    DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF 有权
    大连互连结构及其双重破坏过程

    公开(公告)号：US20080171433A1

    公开(公告)日：2008-07-17

    申请号：US11621996

    申请日：2007-01-11

    Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

    Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

    IPC: H01L21/768

    CPC classification number: H01L21/76811

    Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

    Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。

    Method for programming multi-level cell memory array
    3.
    发明授权
    Method for programming multi-level cell memory array 有权
    多级单元存储器阵列编程方法

    公开(公告)号：US07397705B1

    公开(公告)日：2008-07-08

    申请号：US11670382

    申请日：2007-02-01

    Applicant: Chun Jen Huang ,  Chung Kuang Chen ,  Hsin Yi Ho

    Inventor： Chun Jen Huang ,  Chung Kuang Chen ,  Hsin Yi Ho

    IPC: G11C16/04

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0475 ,  G11C2211/5621

    Abstract: A method for operating a charge-trapping multi-level cell (“MLC”) memory array comprises programming a first plurality of charge-trapping sites to a preliminary first-level value, programming a second plurality of charge-trapping sites to a preliminary second-level value, and programming a third plurality of charge-trapping sites to a final third-level value using a first programming scheme. Then, the first plurality of charge-trapping sites is programmed to a final first-level value and the second plurality of charge-trapping sites is programmed to a final second-level value using a second programming scheme.

    Abstract translation: 用于操作电荷捕获多电平单元（“MLC”）存储器阵列的方法包括将第一多个电荷捕获位点编程为初始第一电平值，将第二多个电荷捕获位点编程到初步第二 并且使用第一编程方案将第三多个电荷捕获位点编程为最终的第三电平值。 然后，将第一组多个电荷捕获位点编程为最终的第一电平值，并且使用第二编程方案将第二多个电荷捕获位置编程为最终的二级值。

    Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content
    4.
    发明授权
    Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content 有权
    使用具有降低的碳含量的基于硅氧烷的氧化硅盖层的双重马氏体过程

    公开(公告)号：US07378343B2

    公开(公告)日：2008-05-27

    申请号：US11164285

    申请日：2005-11-17

    Applicant: Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    Inventor： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    IPC: H01L21/4763

    CPC classification number: H01L21/7681 ,  H01L21/76829

    Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

    Abstract translation: 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

    Structure of Metal Interconnect and Fabrication Method Thereof
    5.
    发明申请
    Structure of Metal Interconnect and Fabrication Method Thereof 有权
    金属互连结构及其制作方法

    公开(公告)号：US20070210454A1

    公开(公告)日：2007-09-13

    申请号：US11748472

    申请日：2007-05-14

    Applicant: Pei-Yu Chou ,  Chun-Jen Huang

    Inventor： Pei-Yu Chou ,  Chun-Jen Huang

    IPC: H01L23/52

    CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

    Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

    Abstract translation: 用于金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体，形成第一介电层和第一图案化硬掩模的基板，以形成第一开口和第二导电体，形成第二导体 电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

    METHOD FOR REMOVING POST-ETCH RESIDUE FROM WAFER SURFACE
    6.
    发明申请
    METHOD FOR REMOVING POST-ETCH RESIDUE FROM WAFER SURFACE 审中-公开
    从表面去除蚀刻后残留物的方法

    公开(公告)号：US20070125750A1

    公开(公告)日：2007-06-07

    申请号：US11674678

    申请日：2007-02-14

    Applicant: Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

    Inventor： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

    IPC: C23F1/00 ,  H01L21/302 ,  B44C1/22

    CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

    Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.

    Abstract translation: 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。

    DUAL DAMASCENE PROCESS UTILIZING TEOS-BASED SILICON OXIDE CAP LAYER HAVING REDUCED CARBON CONTENT
    7.
    发明申请
    DUAL DAMASCENE PROCESS UTILIZING TEOS-BASED SILICON OXIDE CAP LAYER HAVING REDUCED CARBON CONTENT 有权
    使用具有减少碳含量的基于TEOS的氧化硅膜层的双重增塑工艺

    公开(公告)号：US20070111514A1

    公开(公告)日：2007-05-17

    申请号：US11164285

    申请日：2005-11-17

    Applicant: Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    Inventor： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    IPC: H01L21/473

    CPC classification number: H01L21/7681 ,  H01L21/76829

    Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

    Abstract translation: 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

    Asymmetric bidirectional transient voltage suppressor and method of forming same
    8.
    发明申请
    Asymmetric bidirectional transient voltage suppressor and method of forming same 审中-公开
    不对称双向瞬态电压抑制器及其形成方法

    公开(公告)号：US20060216913A1

    公开(公告)日：2006-09-28

    申请号：US11090897

    申请日：2005-03-25

    Applicant: Pu-ju Kung ,  Chun-jen Huang ,  Lung-ching Kao ,  Hung-jieu Peng

    Inventor： Pu-ju Kung ,  Chun-jen Huang ,  Lung-ching Kao ,  Hung-jieu Peng

    IPC: H01L21/20 ,  H01L21/22 ,  H01G9/20

    CPC classification number: H01L29/861 ,  H01L27/0255 ,  H01L29/0607 ,  H01L29/0661 ,  H01L29/86 ,  H01L29/8618

    Abstract: A bi-directional transient voltage suppression device and a method of making same is provided. The method begins by providing a semiconductor substrate of a first conductivity type, and depositing a first epitaxial layer of a second conductivity type opposite the first conductivity type on the substrate. The substrate and the first epitaxial layer form a first p-n junction. A second epitaxial layer having the second conductivity type is deposited on the first epitaxial layer. The second epitaxial layer has a higher dopant concentration than the first epitaxial layer. A third layer having the first conductivity type is formed on the second epitaxial layer. The second epitaxial layer and the third layer form a second p-n junction.

    Abstract translation: 提供双向瞬时电压抑制装置及其制造方法。 该方法开始于提供第一导电类型的半导体衬底，并且在衬底上沉积与第一导电类型相反的第二导电类型的第一外延层。 衬底和第一外延层形成第一p-n结。 具有第二导电类型的第二外延层沉积在第一外延层上。 第二外延层具有比第一外延层更高的掺杂剂浓度。 具有第一导电类型的第三层形成在第二外延层上。 第二外延层和第三层形成第二p-n结。

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