公开(公告)号：US20120286368A1

公开(公告)日：2012-11-15

申请号：US13558109

申请日：2012-07-25

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Abstract translation: 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US20090298243A1

公开(公告)日：2009-12-03

申请号：US12468131

申请日：2009-05-19

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC: H01L21/336

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

Abstract translation: 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20080076215A1

公开(公告)日：2008-03-27

申请号：US11527616

申请日：2006-09-27

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

Abstract translation: 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US20060163734A1

公开(公告)日：2006-07-27

申请号：US11041585

申请日：2005-01-24

Applicant: Kong-Beng Thei ,  Chung-Long Cheng ,  Chung-Shi Liu ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Chung-Long Cheng ,  Chung-Shi Liu ,  Harry Chuang

IPC: H01L23/48

CPC classification number: H01L23/5258 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.

Abstract translation: 提供了一种熔丝结构和用于制造熔丝结构的方法。 在一个示例中，该方法包括在半导体衬底上提供多层互连结构（MLI）。 MLI包括多个保险丝连接和接合连接功能。 钝化层形成在MLI上方并被图案化以形成开口，其中每个开口与保险丝连接或接合连接特征中的一个对准。 在钝化层和开口中形成导电层。 将导电层图案化以形成结合特征和熔丝结构。 每个接合特征与接合连接特征之一接触，并且每个熔断器结构与两个熔断器连接特征接触。 在熔丝结构之上形成盖电介质层，并将其图案化以暴露粘合特征中的至少一个，同时保留熔丝结构。

公开(公告)号：US08629050B2

公开(公告)日：2014-01-14

申请号：US13443550

申请日：2012-04-10

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry-Hak-Lay Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry-Hak-Lay Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC: H01L21/02

CPC classification number: H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract translation: 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US08237201B2

公开(公告)日：2012-08-07

申请号：US11807654

申请日：2007-05-30

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC: H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Abstract translation: 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US07812379B2

公开(公告)日：2010-10-12

申请号：US12468137

申请日：2009-05-19

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC: H01L29/78

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

Abstract translation: 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在没有被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20100078728A1

公开(公告)日：2010-04-01

申请号：US12546475

申请日：2009-08-24

Applicant: Hou-Ju Li ,  Chung Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Hou-Ju Li ,  Chung Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823425 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848

Abstract: The present disclosure provides an integrated circuit having metal gate stacks. The integrated circuit includes a semiconductor substrate; a gate stack disposed on the semiconductor substrate, wherein the gate stack includes a high k dielectric layer and a first metal layer disposed on the high k dielectric layer; and a raised source/drain region configured on a side of the gate stack and formed by an epitaxy process, wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the raised source/drain region.

Abstract translation: 本公开提供了具有金属栅极堆叠的集成电路。 集成电路包括半导体衬底; 设置在所述半导体衬底上的栅极堆叠，其中所述栅极堆叠包括高k电介质层和设置在所述高k电介质层上的第一金属层; 以及构造在所述栅极堆叠侧并通过外延工艺形成的凸起的源极/漏极区域，其中所述半导体衬底包括位于所述升高的源极/漏极区域下方的硅锗（SiGe）特征。

公开(公告)号：US07678636B2

公开(公告)日：2010-03-16

申请号：US11520377

申请日：2006-09-13

Applicant: Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

Inventor： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

IPC: H01L21/8238 ,  H01L21/337

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/7843

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

Abstract translation: 一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成 在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。 在具有NMOS器件的区域中，相同的应力记忆层没有减小。 在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

公开(公告)号：US07525177B2

公开(公告)日：2009-04-28

申请号：US11097743

申请日：2005-04-01

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Yuan Lin

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Yuan Lin

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/417

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

Abstract translation: 一种用于改善CMP工艺并改善与有源区的电隔离的虚拟区域变容二极管及其形成方法，所述变容二极管包括具有虚拟区域的半导体衬底，所述虚拟区域包括具有第一极性的第一阱区; 布置在所述虚拟区域中的浅沟槽隔离（STI）结构，其限定包括第一，第二和第三台面区域的相邻台面区域; 具有第二极性的第二阱区，其具有第二极性的第一台面区域，以形成PN结界面; 其中具有第一极性的所述第二和第三台面区域形成在所述第一台面区域的两侧附近。