公开(公告)号：US08546860B2

公开(公告)日：2013-10-01

申请号：US13494769

申请日：2012-06-12

Applicant: Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

Inventor： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC: H01L31/113 ,  H01L31/173

CPC classification number: H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

Abstract: This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.

Abstract translation: 本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。 有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。 有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。 有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色 细胞计数由第一次压力引起。

公开(公告)号：US20120043618A1

公开(公告)日：2012-02-23

申请号：US13284594

申请日：2011-10-28

Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC: H01L27/092

CPC classification number: G06F17/5068 ,  G03F1/36

Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

Abstract translation: 通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。 因此，可以在不违反设计规则的情况下改善两种装置的应力性能。

公开(公告)号：US07943961B2

公开(公告)日：2011-05-17

申请号：US12048135

申请日：2008-03-13

Applicant: Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

Inventor： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC: H01L23/48

CPC classification number: H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract translation: 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

公开(公告)号：US07825477B2

公开(公告)日：2010-11-02

申请号：US11738968

申请日：2007-04-23

Applicant: Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

Inventor： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC: H01L23/62 ,  H01L29/78 ,  H01L21/0234

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract translation: 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US07732298B2

公开(公告)日：2010-06-08

申请号：US11669870

申请日：2007-01-31

Applicant: Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

Inventor： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC: H01L21/76

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/665

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract translation: 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US20090230439A1

公开(公告)日：2009-09-17

申请号：US12048135

申请日：2008-03-13

Applicant: Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

Inventor： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC: H01L29/00

CPC classification number: H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract translation: 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

公开(公告)号：US20080119023A1

公开(公告)日：2008-05-22

申请号：US11600030

申请日：2006-11-16

Applicant: Chung-Te Lin ,  Di-Houng Lee ,  Yee-Chaung See

Inventor： Chung-Te Lin ,  Di-Houng Lee ,  Yee-Chaung See

IPC: H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a first conductivity type that is the same as that of the substrate, is implanted at first and second angles in both the first and second regions to form halo regions only in source sides under the gate structures in the first region and in both source and drain sides under the gate structures in the second region.

公开(公告)号：US06797587B1

公开(公告)日：2004-09-28

申请号：US10641445

申请日：2003-08-13

Applicant: Feng-Cheng Yang ,  Chung-Te Lin ,  Yea-Dean Sheu ,  Chih-Hung Wang

Inventor： Feng-Cheng Yang ,  Chung-Te Lin ,  Yea-Dean Sheu ,  Chih-Hung Wang

IPC: H01L2176

CPC classification number: H01L21/76237 ,  H01L21/823481

Abstract: Within a method for forming an isolation region within a semiconductor substrate, there is, prior to forming the isolation region within an isolation trench formed adjoining an active region of a semiconductor substrate, implanted a dopant into a corner of the active region. The corner of the active region is uncovered by laterally etching an isolation trench mask to form a laterally etched isolation trench mask which serves as an ion implantation mask layer when implanting the dopant into the corner of the active region. The method provides for enhanced performance, and minimal affect of a semiconductor device formed within the active region of the semiconductor substrate.

Abstract translation: 在用于在半导体衬底内形成隔离区域的方法中，在形成邻接半导体衬底的有源区域的隔离沟槽内形成隔离区之前，将掺杂剂注入有源区的角部。 通过横向蚀刻隔离沟槽掩模来形成有源区域的角部，以形成横向蚀刻的隔离沟槽掩模，当将掺杂剂注入到有源区域的角部中时，其作为离子注入掩模层。 该方法提供了在半导体衬底的有源区域内形成的半导体器件的增强性能和最小的影响。

公开(公告)号：US06790756B2

公开(公告)日：2004-09-14

申请号：US10385954

申请日：2003-03-11

Applicant: Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

Inventor： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

IPC: H01L213205

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Abstract translation: 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

Applicant: Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

Inventor： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC: H01L21326

CPC classification number: H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

Abstract translation: 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。