公开(公告)号：US07666792B2

公开(公告)日：2010-02-23

申请号：US12035443

申请日：2008-02-22

申请人： Chung-Yen Chou ,  Hai-Han Hung ,  Teng-Wang Huang ,  Shin-Yu Nieh

发明人： Chung-Yen Chou ,  Hai-Han Hung ,  Teng-Wang Huang ,  Shin-Yu Nieh

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L27/1087 ,  H01L29/66181

摘要： The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.

摘要翻译： 本发明提供了一种在衬底中形成深沟槽的方法。 首先使用牺牲层和衬垫层来限定深沟槽图案。 然后用硅玻璃层代替牺牲层。 厚掩模层包括硅玻璃层，衬底层和氮化硅层形成在衬底上。 通过厚掩模层的开口，将深沟槽蚀刻到衬底中。

公开(公告)号：US20090130853A1

公开(公告)日：2009-05-21

申请号：US12035443

申请日：2008-02-22

申请人： Chung-Yen Chou ,  Hai-Han Hung ,  Teng-Wang Huang ,  Shin-Yu Nieh

发明人： Chung-Yen Chou ,  Hai-Han Hung ,  Teng-Wang Huang ,  Shin-Yu Nieh

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L27/1087 ,  H01L29/66181

摘要： The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.

摘要翻译： 本发明提供了一种在衬底中形成深沟槽的方法。 首先使用牺牲层和衬垫层来限定深沟槽图案。 然后用硅玻璃层代替牺牲层。 厚掩模层包括硅玻璃层，衬底层和氮化硅层形成在衬底上。 通过厚掩模层的开口，将深沟槽蚀刻到衬底中。

公开(公告)号：US07025858B2

公开(公告)日：2006-04-11

申请号：US10378230

申请日：2003-03-03

申请人： Chung-Yen Chou

发明人： Chung-Yen Chou

IPC分类号： H01L21/00 ,  C23C16/00

CPC分类号： H01L21/6833 ,  Y10S156/915 ,  Y10T279/23

摘要： The present invention provides an apparatus for supporting a wafer in a semiconductor process. The apparatus includes an electrostatic chuck, a focus ring and a conductive material. The electrostatic chuck has a first fillister in its periphery. When a DC power is applied to the electrostatic chuck, the wafer is attached tightly to the electrostatic chuck by electromagnetic force. The focus ring has a second fillister opposite to the first fillister, and the focus ring is fixed on the periphery of the electrostatic chuck. The conductive material is located below the focus ring, and the conductive material is moving between the first fillister and the second fillister by a drive apparatus. When the conductive material is moving close to the focus ring in semiconductor etching process, it can improve the etching uniformity of the wafer periphery.

摘要翻译： 本发明提供一种用于在半导体工艺中支撑晶片的装置。 该装置包括静电卡盘，聚焦环和导电材料。 静电吸盘在其周边具有第一填充物。 当向静电卡盘施加直流电力时，晶片通过电磁力紧紧地附着在静电卡盘上。 聚焦环具有与第一填充物相对的第二填充物，并且聚焦环固定在静电卡盘的周边上。 导电材料位于聚焦环下方，导电材料通过驱动装置在第一填充器和第二填充器之间移动。 当导电材料在半导体蚀刻工艺中靠近聚焦环移动时，可以提高晶片周边的蚀刻均匀性。

公开(公告)号：US08643074B2

公开(公告)日：2014-02-04

申请号：US13462427

申请日：2012-05-02

申请人： Chih-Yang Pai ,  Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chung-Yen Chou

发明人： Chih-Yang Pai ,  Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chung-Yen Chou

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶部电极，底部电极和介于 所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

公开(公告)号：US20130292794A1

公开(公告)日：2013-11-07

申请号：US13462427

申请日：2012-05-02

申请人： Chih-Yang PAI ,  Kuo-Chi TU ,  Wen-Chuan CHIANG ,  Chung-Yen CHOU

发明人： Chih-Yang PAI ,  Kuo-Chi TU ,  Wen-Chuan CHIANG ,  Chung-Yen CHOU

IPC分类号： H01L29/92 ,  H01L21/762

CPC分类号： H01L28/91 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶电极，底电极和介于 所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

公开(公告)号：US08501566B1

公开(公告)日：2013-08-06

申请号：US13609289

申请日：2012-09-11

申请人： Chung-Yen Chou ,  Tieh-Chiang Wu ,  Hsin-Jung Ho

发明人： Chung-Yen Chou ,  Tieh-Chiang Wu ,  Hsin-Jung Ho

IPC分类号： H01L21/336

CPC分类号： H01L27/10876

摘要： A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.

摘要翻译： 提供了一种用于制造凹陷通道存取晶体管器件的方法。 提供其上具有凹部的半导体衬底。 在凹部中形成栅介质层。 然后将栅极材料层沉积到凹部中。 在栅极材料层上形成电介质盖层。 蚀刻电介质盖层和栅极材料层以形成栅极图案。 然后在栅极图案上形成衬里层。 在栅极图案的每个侧壁上的衬垫层上形成间隔物。 蚀刻没有被间隔物掩蔽的衬垫层以形成露出栅极材料层的一部分的底切凹部。 然后移除间隔物。 在底切凹部中的栅极材料层的暴露部分被氧化以在其中形成绝缘块。