公开(公告)号：US09245895B2

公开(公告)日：2016-01-26

申请号：US13190565

申请日：2011-07-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US09159568B2

公开(公告)日：2015-10-13

申请号：US11639666

申请日：2006-12-15

申请人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66537 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

摘要翻译： 公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。 所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。 此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件 第二元件的侧壁。 形成与第一存储元件和第二存储元件接触的字线。

公开(公告)号：US08564042B2

公开(公告)日：2013-10-22

申请号：US11702845

申请日：2007-02-05

申请人： Fred Cheung ,  Hiroyuki Kinoshita ,  Chungho Lee ,  Yu Sun ,  Chi Chang

发明人： Fred Cheung ,  Hiroyuki Kinoshita ,  Chungho Lee ,  Yu Sun ,  Chi Chang

IPC分类号： H01L29/94

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括第一电荷存储元件和第二电荷存储元件，其中第一和第二电荷存储元件包括氮化物。 存储单元还包括形成在第一和第二电荷存储元件之间的绝缘层。 绝缘层提供第一和第二电荷存储元件之间的绝缘。

公开(公告)号：US20130098435A1

公开(公告)日：2013-04-25

申请号：US13653938

申请日：2012-10-17

申请人： Zhibo Zhao ,  Benyamin Buller ,  Chungho Lee ,  Markus Gloeckler ,  David Hwang ,  Scott Mills ,  Rui Shao

发明人： Zhibo Zhao ,  Benyamin Buller ,  Chungho Lee ,  Markus Gloeckler ,  David Hwang ,  Scott Mills ,  Rui Shao

IPC分类号： H01L31/0224 ,  H01L31/18

CPC分类号： H01L31/022466 ,  B82Y30/00 ,  H01L31/0488 ,  H01L31/1884 ,  Y02E10/50

摘要： Described herein is a contact for a photovoltaic device and method of making the same. The contact has a transparent conductive oxide stack, where a first portion of the transparent conductive oxide stack is formed by atmospheric pressure vapor deposition and a second portion of the transparent conductive oxide stack is formed by physical vapor deposition.

摘要翻译： 这里描述的是用于光伏器件的接触件及其制造方法。 接触件具有透明导电氧化物堆叠，其中透明导电氧化物堆叠的第一部分通过大气压气相沉积形成，并且透明导电氧化物堆叠的第二部分通过物理气相沉积形成。

公开(公告)号：US20100283100A1

公开(公告)日：2010-11-11

申请号：US12840165

申请日：2010-07-20

申请人： Chungho LEE ,  Ashot MELIK-MARTIROSIAN ,  Wei ZHENG ,  Timothy THURGATE ,  Chi CHANG ,  Hiroyuki KINOSHITA ,  Kuo-Tung CHANG ,  Unsoon KIM

发明人： Chungho LEE ,  Ashot MELIK-MARTIROSIAN ,  Wei ZHENG ,  Timothy THURGATE ,  Chi CHANG ,  Hiroyuki KINOSHITA ,  Kuo-Tung CHANG ,  Unsoon KIM

IPC分类号： H01L29/792

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07666739B2

公开(公告)日：2010-02-23

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US07622373B2

公开(公告)日：2009-11-24

申请号：US11615563

申请日：2006-12-22

申请人： Wei Zheng ,  Chungho Lee

发明人： Wei Zheng ,  Chungho Lee

IPC分类号： H01L21/425

CPC分类号： H01L29/792 ,  H01L21/7624

摘要： A memory device includes a substrate, a first gate stack overlying the substrate, a second gate stack overlying the substrate and spaced apart from the first gate stack, an oxide region formed at a first depth within the substrate and between the first and second gate stacks, and an impurity doped region formed at a second depth within the substrate and between the first and second gate stacks, the first depth being lower than the second depth.

摘要翻译： 存储器件包括衬底，覆盖衬底的第一栅极堆叠，覆盖衬底并与第一栅极堆叠隔开的第二栅极堆叠，形成在衬底内的第一深度处以及在第一和第二栅极堆叠之间的氧化物区域 以及杂质掺杂区域，其形成在衬底内的第二深度处，并且在第一和第二栅极堆叠之间，第一深度低于第二深度。

公开(公告)号：US20090108330A1

公开(公告)日：2009-04-30

申请号：US11924169

申请日：2007-10-25

申请人： Minghao Shen ,  Chungho Lee ,  Hiroyuki Kinoshita ,  Huaqiang Wu

发明人： Minghao Shen ,  Chungho Lee ,  Hiroyuki Kinoshita ,  Huaqiang Wu

IPC分类号： H01L29/792 ,  H01L21/3205

CPC分类号： H01L29/7923 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11568

摘要： Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

摘要翻译： 提供了包含半导体衬底上的两个分裂子光刻电荷存储节点的存储单元以及用于制造存储单元的方法。 这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。 通过在间隔物的倾斜侧表面或外表面之间除去第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。 此外，通过去除间隔物的倾斜侧表面或外表面之间的电荷存储层的暴露部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个分裂的亚光刻电荷存储节点。

公开(公告)号：US20090061631A1

公开(公告)日：2009-03-05

申请号：US11848515

申请日：2007-08-31

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

IPC分类号： H01L21/311

CPC分类号： H01L29/7923 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

摘要翻译： 提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。 该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。 可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

公开(公告)号：US07432156B1

公开(公告)日：2008-10-07

申请号：US11409361

申请日：2006-04-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。