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    Modified via bottom structure for reliability enhancement
    3.
    发明授权
    Modified via bottom structure for reliability enhancement 有权
    通过底部结构改进可靠性增强

    公开(公告)号：US07282802B2

    公开(公告)日：2007-10-16

    申请号：US10964882

    申请日：2004-10-14

    申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

    摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

    Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process
    5.
    发明授权
    Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process 有权
    用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）沟道应变

    公开(公告)号：US08492208B1

    公开(公告)日：2013-07-23

    申请号：US13344352

    申请日：2012-01-05

    申请人： Guy Cohen ,  Michael A. Guillorn ,  Conal Eugene Murray

    发明人： Guy Cohen ,  Michael A. Guillorn ,  Conal Eugene Murray

    IPC分类号： H01L21/00 ,  H01L29/76

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439

    摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

    摘要翻译： 提供一种制造FET器件的方法，其包括以下步骤。 纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。 沉积围绕纳米线的HSQ层。 围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。 形成一个或多个保持在纳米线中诱发的应变的栅极。 还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域， 其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

    Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process
    8.
    发明申请
    Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process 有权
    用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）通道应变

    公开(公告)号：US20130175503A1

    公开(公告)日：2013-07-11

    申请号：US13344352

    申请日：2012-01-05

    申请人： Guy Cohen ,  Michael A. Guillorn ,  Conal Eugene Murray

    发明人： Guy Cohen ,  Michael A. Guillorn ,  Conal Eugene Murray

    IPC分类号： H01L29/775 ,  H01L21/336 ,  B82Y99/00 ,  B82Y40/00

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439

    摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

    摘要翻译： 提供一种制造FET器件的方法，其包括以下步骤。 纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。 沉积围绕纳米线的HSQ层。 围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。 形成一个或多个保持在纳米线中诱发的应变的栅极。 还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域， 其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。