Time Interleaving Analog-to-Digital Converter
    1.
    发明申请
    Time Interleaving Analog-to-Digital Converter 有权
    时间交错模数转换器

    公开(公告)号:US20140152477A1

    公开(公告)日:2014-06-05

    申请号:US13706035

    申请日:2012-12-05

    IPC分类号: H03M1/50 H03M1/12

    摘要: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

    摘要翻译: 时间交织模数转换器(ADC)包括多个ADC; 定时发生器,用于为每个ADC产生时钟信号,使得所述时钟信号的边沿触发ADC的输入信号的采样; 以及定时调整电路,用于在由ADC接收时钟信号之前接收和调整时钟信号,使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 以及用于调整多个ADC的带宽的电路。

    Time-interleaved analog-to-digital converter bandwidth matching
    2.
    发明授权
    Time-interleaved analog-to-digital converter bandwidth matching 有权
    时间交织的模数转换器带宽匹配

    公开(公告)号:US09071270B2

    公开(公告)日:2015-06-30

    申请号:US13906590

    申请日:2013-05-31

    摘要: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.

    摘要翻译: 时间交织的模数转换器(ADC)包括一组时间多路复用子ADC电路,每个子ADC电路包括采样和保持电路。 每个采样和保持电路包括一个自举电路,用于在开关的输入端和开关的栅极端之间保持恒定的电压电平,用于在轨道模式和保持模式之间切换的开关以及电容器组相关联 其中自举电路使得电容器组的设置影响电压电平。

    Randomized time-interleaved sample-and-hold system
    3.
    发明授权
    Randomized time-interleaved sample-and-hold system 有权
    随机时间交错采样和保持系统

    公开(公告)号:US08890729B2

    公开(公告)日:2014-11-18

    申请号:US13751062

    申请日:2013-01-26

    IPC分类号: H03M1/10 H03M1/12

    摘要: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

    摘要翻译: 时间交织模数转换器(ADC)包括多个ADC; 定时发生器,其为所述多个ADC中的每一个产生停靠信号,使得所述时钟信号的边沿触发所述多个ADC对输入信号的采样; 以及定时调整电路,用于在由ADC接收对接信号之前接收和调整停靠信号,使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 和随机数发生器,伪随机选择哪个ADC采样输入信号; 以及用于调整多个ADC的带宽的电路。

    RANDOMIZED TIME-INTERLEAVED SAMPLE-AND-HOLD SYSTEM
    4.
    发明申请
    RANDOMIZED TIME-INTERLEAVED SAMPLE-AND-HOLD SYSTEM 有权
    随机时间间隔采样和保持系统

    公开(公告)号:US20140152478A1

    公开(公告)日:2014-06-05

    申请号:US13751062

    申请日:2013-01-26

    IPC分类号: H03M1/12

    摘要: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

    摘要翻译: 时间交织模数转换器(ADC)包括多个ADC; 定时发生器,其为所述多个ADC中的每一个产生停靠信号,使得所述时钟信号的边沿触发所述多个ADC对输入信号的采样; 以及定时调整电路,用于在由ADC接收对接信号之前接收和调整停靠信号,使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 和随机数发生器,伪随机选择哪个ADC采样输入信号; 以及用于调整多个ADC的带宽的电路。

    TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER BANDWIDTH MATCHING
    5.
    发明申请
    TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER BANDWIDTH MATCHING 有权
    时间间隔模数转换器带宽匹配

    公开(公告)号:US20130265182A1

    公开(公告)日:2013-10-10

    申请号:US13906590

    申请日:2013-05-31

    IPC分类号: H03M1/54

    摘要: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.

    摘要翻译: 时间交织的模数转换器(ADC)包括一组时间多路复用子ADC电路,每个子ADC电路包括采样和保持电路。 每个采样和保持电路包括一个自举电路,用于在开关的输入端和开关的栅极端之间保持恒定的电压电平,用于在轨道模式和保持模式之间切换的开关以及电容器组相关联 其中自举电路使得电容器组的设置影响电压电平。

    Time interleaving analog-to-digital converter
    6.
    发明授权
    Time interleaving analog-to-digital converter 有权
    时间交织模数转换器

    公开(公告)号:US08890739B2

    公开(公告)日:2014-11-18

    申请号:US13706035

    申请日:2012-12-05

    IPC分类号: H03M1/36 H03M1/50 H03M1/12

    摘要: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

    摘要翻译: 时间交织模数转换器(ADC)包括多个ADC; 定时发生器,用于为每个ADC产生时钟信号,使得所述时钟信号的边沿触发ADC的输入信号的采样; 以及定时调整电路,用于在由ADC接收时钟信号之前接收和调整时钟信号,使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 以及用于调整多个ADC的带宽的电路。