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公开(公告)号:US12198051B2
公开(公告)日:2025-01-14
申请号:US18096198
申请日:2023-01-12
Applicant: D-WAVE SYSTEMS INC.
Inventor: William G. Macready , Jason T. Rolfe
IPC: G06N3/047 , G06F18/214 , G06N3/045 , G06N3/08 , G06N10/00
Abstract: Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
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公开(公告)号:US12099901B2
公开(公告)日:2024-09-24
申请号:US18243280
申请日:2023-09-07
Applicant: D-WAVE SYSTEMS INC.
Inventor: Richard G. Harris
CPC classification number: G06N10/00 , G06F15/7867 , G06N10/40
Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
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公开(公告)号:US20240256930A1
公开(公告)日:2024-08-01
申请号:US18514482
申请日:2023-11-20
Applicant: D-WAVE SYSTEMS INC.
Inventor: Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号:US20240070497A1
公开(公告)日:2024-02-29
申请号:US18243280
申请日:2023-09-07
Applicant: D-WAVE SYSTEMS INC.
Inventor: Richard G. Harris
CPC classification number: G06N10/00 , G06F15/7867 , G06N10/40
Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
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公开(公告)号:US11900264B2
公开(公告)日:2024-02-13
申请号:US16785125
申请日:2020-02-07
Applicant: D-WAVE SYSTEMS INC.
Inventor: Catherine McGeoch , William W. Bernoudy
IPC: G06N5/01 , G06F15/163 , G06F17/18 , G06N10/00
CPC classification number: G06N5/01 , G06F15/163 , G06F17/18 , G06N10/00
Abstract: Hybrid quantum-classical approaches for solving computational problems in which results from a quantum processor are combined with an exact method executed on a classical processor are described. Quantum processors can generate candidate solutions to a combinatorial optimization problem, but since quantum processors can be probabilistic, they are unable to certify that a solution is an optimal solution. A hybrid quantum-classical exact solver addresses this problem by combining outputs from a quantum annealing processor with a classical exact algorithm that is modified to exploit properties of the quantum computation. The exact method executed on a classical processor can be a Branch and Bound algorithm. A Branch and Bound algorithm can be modified to exploit properties of quantum computation including a) the sampling of multiple low-energy solutions by a quantum processor, and b) the embedding of solutions in a regular structure such as a native hardware graph of a quantum processor.
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公开(公告)号:US11900216B2
公开(公告)日:2024-02-13
申请号:US17988250
申请日:2022-11-16
Applicant: D-WAVE SYSTEMS INC.
Inventor: James A. King , William W. Bernoudy , Kelly T. R. Boothby , Pau Farré Pérez
IPC: G06N10/00 , G06F17/18 , G06F18/21 , G06F18/23213
CPC classification number: G06N10/00 , G06F17/18 , G06F18/217 , G06F18/23213
Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
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公开(公告)号:US20230370069A1
公开(公告)日:2023-11-16
申请号:US17883874
申请日:2022-08-09
Applicant: D-WAVE SYSTEMS INC.
Inventor: Mohammad H. Amin , Richard G. Harris
IPC: H03K19/195 , G06N10/40
CPC classification number: H03K19/195 , G06N10/40
Abstract: A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.
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公开(公告)号:US20230316094A1
公开(公告)日:2023-10-05
申请号:US18126566
申请日:2023-03-27
Applicant: D-WAVE SYSTEMS INC.
Inventor: Pau Farré Pérez , Jack R. Raymond
CPC classification number: G06N5/01 , G06N10/40 , G06F9/44505
Abstract: A heuristic solver is wrapped in a meta algorithm that will perform multiple sub-runs within the desired time limit, and expand or reduce the effort based on the time it has taken so far and the time left. The goal is to use the largest effort possible as this typically increases the probability of success. In another implementation, the meta algorithm iterates the time-like parameter from a small value, and determine the next test-value so as to minimize time to target collecting data at large effort only as necessary. The meta algorithm evaluates the energy of the solutions obtained to determine whether to increase or decrease the value of the time-like parameter. The heuristic algorithm may be Simulated Annealing, the heuristic algorithm may run on a quantum processor, including a quantum annealing processor or a gate-model quantum processor.
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公开(公告)号:US11730066B2
公开(公告)日:2023-08-15
申请号:US17399375
申请日:2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor: Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号:US20230222337A1
公开(公告)日:2023-07-13
申请号:US18096198
申请日:2023-01-12
Applicant: D-WAVE SYSTEMS INC.
Inventor: William G. Macready , Jason T. Rolfe
CPC classification number: G06N3/08 , G06N10/00 , G06N3/045 , G06F18/2148
Abstract: Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
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