公开(公告)号：US06198306B1

公开(公告)日：2001-03-06

申请号：US09121957

申请日：1998-07-24

申请人： D. C. Sessions

发明人： D. C. Sessions

IPC分类号： H03K19094

CPC分类号： H03K19/0013

摘要： A CMOS wave shaping buffer circuit comprises two CMOS inverter stages connected as a non-inverting buffer. In addition, the two stages are further coupled by way of their supply connections to produce a positive feedback from the second stage to the first whenever both stages are driven to a linear state, that is both transistors of each stage are “ON”. The positive feedback prevents the output stage from remaining in a logically ambiguous state, but forces crisp transitions from one state to another even for slowly changing input signals.

摘要翻译： CMOS波形整形缓冲电路包括作为非反相缓冲器连接的两个CMOS反相器级。 此外，两级通过它们的电源连接进一步耦合，以便每两级驱动到线性状态，即每级的两个晶体管均为“ON”，从而产生从第二级到第一级的正反馈。 正反馈防止输出级保持在逻辑上不明确的状态，但是即使对于缓慢变化的输入信号，也会强制从一种状态到另一种状态的清晰转换。

公开(公告)号：US6154018A

公开(公告)日：2000-11-28

申请号：US388034

申请日：1999-09-01

申请人： D. C. Sessions

发明人： D. C. Sessions

IPC分类号： H01L21/822 ,  G05F3/26 ,  H01L27/04 ,  H03F3/343 ,  H03F3/45 ,  G05F3/16

CPC分类号： G05F3/262

摘要： A high differential impedance load device. The present invention recites a load device including a first lead, a second lead, a first current mirror, a second current mirror, and a third lead. First lead, second lead, and third lead are coupled to first current mirror and second current mirror such that a current sunk on first lead is approximately equal to a current sunk on second lead. Third lead represents a reference voltage which is ground.

摘要翻译： 高差分阻抗负载装置。 本发明描述了包括第一引线，第二引线，第一电流镜，第二电流镜和第三引线的负载装置。 第一引线，第二引线和第三引线耦合到第一电流镜和第二电流镜，使得第一引线上的电流近似等于在第二引线上的电流下降。 第三导线代表接地的参考电压。

公开(公告)号：US5994925A

公开(公告)日：1999-11-30

申请号：US59631

申请日：1998-04-13

申请人： D. C. Sessions

发明人： D. C. Sessions

IPC分类号： H03K19/003 ,  A03K19/094

CPC分类号： H03K19/00384

摘要： A pseudo-differential receiver is described which includes a bias generator circuit portion for providing a bias signal to a receiver circuit portion. The bias generator includes first and second load devices for establishing bias voltages at first and second nodes and also includes a first CMOS inverter biased by and coupled between the first and second nodes. The input of the first inverter is coupled to a reference voltage and the output of the inverter provides a bias voltage which is fed back to the gates of the first and second load devices. The biasing conditions on the first and second nodes bias the first inverter such that the threshold voltage of the first CMOS inverter is equal to the reference voltage. The biasing signal is used to bias loading devices in the receiver circuit portion. The receiver circuit portion includes loading and inverter devices that are electrically matched to the loading and inverter devices in the bias generator circuit portion. As a result, the bias signal biases the receiver circuit loading devices such that the receiver circuit has the same threshold as the bias generator circuit which is equal to the input reference voltage coupled to the bias generator. The bias voltage provided by the bias generator can be used to bias other receiver circuit so as to minimize input receiver size and current in larger integrated circuit designs.

摘要翻译： 描述了一种伪差分接收机，其包括用于向接收机电路部分提供偏置信号的偏置发生器电路部分。 偏置发生器包括用于在第一和第二节点处建立偏置电压的第一和第二负载装置，并且还包括由第一和第二节点偏置并耦合在第一和第二节点之间的第一CMOS反相器。 第一反相器的输入耦合到参考电压，并且反相器的输出提供反馈到第一和第二负载装置的栅极的偏置电压。 第一和第二节点上的偏置条件偏置第一反相器，使得第一CMOS反相器的阈值电压等于参考电压。 偏置信号用于偏置接收器电路部分中的加载装置。 接收器电路部分包括与偏置发生器电路部分中的负载和逆变器装置电气匹配的装载和逆变器装置。 结果，偏置信号偏置接收器电路加载装置，使得接收器电路具有与偏置发生器电路相同的阈值，其等于耦合到偏置发生器的输入参考电压。 由偏置发生器提供的偏置电压可用于偏置其他接收器电路，以便在较大集成电路设计中使输入接收器尺寸和电流最小化。

公开(公告)号：US5933041A

公开(公告)日：1999-08-03

申请号：US787768

申请日：1997-01-28

申请人： D. C. Sessions ,  Sung-Hun Oh ,  Elie Georges Khoury

发明人： D. C. Sessions ,  Sung-Hun Oh ,  Elie Georges Khoury

IPC分类号： H03K19/00 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0005

摘要： An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

摘要翻译： 一种改进的输出驱动器，通过产生恒定的源阻抗来最大限度地减少在传输线上驱动信号时的源极点反射。 改进的输出驱动器使用晶体管开关电路来在晶体管开关电路被使能并且不在饱和模式下工作时产生几乎恒定的通道阻抗。 当施加足够的电压来施加开关二极管电路时，开关二极管电路并联耦合到晶体管开关电路，用于产生几乎恒定的源极阻抗。 控制电路耦合到晶体管开关电路和开关二极管电路两者，用于启用和禁用晶体管开关电路和开关二极管电路。 通过交替地启用和禁用晶体管开关电路和开关二极管电路，控制电路能够产生恒定的源阻抗。

公开(公告)号：US07085950B2

公开(公告)日：2006-08-01

申请号：US09966297

申请日：2001-09-28

申请人： Gregory E. Ehmann ,  D. C. Sessions ,  Timothy Pontius

发明人： Gregory E. Ehmann ,  D. C. Sessions ,  Timothy Pontius

IPC分类号： G06F13/14 ,  G06F1/24

CPC分类号： H04L7/0008 ,  H04L25/14

摘要： A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

公开(公告)号：US06606576B2

公开(公告)日：2003-08-12

申请号：US09766308

申请日：2001-01-19

申请人： D. C. Sessions

发明人： D. C. Sessions

IPC分类号： G01D1800

CPC分类号： G06F13/423

摘要： A method and arrangement of transferring data at high speeds over a parallel data bus provides for calibration of the data without interrupting the data communication. Consistent with one aspect of the present invention, a method of parallel data communication is provided for a circuit arrangement including a parallel arrangement of data paths for passing data in parallel between at least two nodes. The method compares a sequence of data over an additional calibration/spare path relative to a matched sequence of data being passed on one of the multiple paths. In response to detecting skewed data, the transmission time for the subject path is adjusted in response to the comparison. Other example aspects of the invention are directed to procedures for rotating the calibration procedure through each of the data paths while using the spare to maintain communication integrity, and various embodiments for controlling the calibration procedure and for detecting whether the data is skewed.

公开(公告)号：US6166580A

公开(公告)日：2000-12-26

申请号：US216701

申请日：1998-12-18

申请人： D. C. Sessions

发明人： D. C. Sessions

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H01L27/0922

摘要： A voltage-buffer circuit for changing an input signal at a first voltage range to an output signal at a second voltage range. In one embodiment, the voltage-buffer circuit is comprised of an input lead for receiving an input signal at a first voltage range, a plurality of transistors coupled to the input lead, and an output lead coupled to the plurality of transistors. The purpose of the transistors is to convert the input signal at the first voltage range to an output signal at a second voltage range. The output lead is for receiving the output signal at the second voltage range from said plurality of transistors. The plurality of transistors are arranged into a plurality of stages, with at least one of the transistors having a gate oxide of a first thickness and at least one of the transistors having a gate oxide of a second thickness, where the first thickness is less than said second thickness.

摘要翻译： 一种用于将第一电压范围内的输入信号改变为第二电压范围的输出信号的电压缓冲电路。 在一个实施例中，电压缓冲电路包括用于接收第一电压范围的输入信号的输入引线，耦合到输入引线的多个晶体管以及耦合到多个晶体管的输出引线。 晶体管的目的是将第一电压范围内的输入信号转换成第二电压范围的输出信号。 输出引线用于从所述多个晶体管接收在第二电压范围的输出信号。 多个晶体管被布置成多个级，其中至少一个晶体管具有第一厚度的栅极氧化物，并且至少一个晶体管具有第二厚度的栅极氧化物，其中第一厚度小于 第二厚度。

公开(公告)号：US08825912B2

公开(公告)日：2014-09-02

申请号：US12564493

申请日：2009-09-22

申请人： Gregg Lahti ,  Rodney Pesavento ,  Joseph W. Triece ,  D. C. Sessions

发明人： Gregg Lahti ,  Rodney Pesavento ,  Joseph W. Triece ,  D. C. Sessions

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12

CPC分类号： G06F13/124 ,  G06F13/28 ,  Y02D10/14

摘要： A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

摘要翻译： 微控制器或集成系统具有总线，与总线耦合的多个外围设备，非易失性存储器和与非易失性存储器耦合的状态机，并且可操作以通过读取初始化信息来初始化外围设备 从非易失性存储器写入外围设备。

公开(公告)号：US06636166B2

公开(公告)日：2003-10-21

申请号：US09871197

申请日：2001-05-31

申请人： D. C. Sessions ,  Robert J. Caesar, Jr. ,  Ivan Svestka ,  David R. Evoy ,  Timothy Pontius ,  Mark Johnson ,  Arjan Bink

发明人： D. C. Sessions ,  Robert J. Caesar, Jr. ,  Ivan Svestka ,  David R. Evoy ,  Timothy Pontius ,  Mark Johnson ,  Arjan Bink

IPC分类号： H03M700

CPC分类号： H04L25/4908 ,  H04L25/14

摘要： In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

公开(公告)号：US5828249A

公开(公告)日：1998-10-27

申请号：US762770

申请日：1996-12-10

申请人： D. C. Sessions

发明人： D. C. Sessions

IPC分类号： H03K3/356 ,  H03K21/117

CPC分类号： H03K3/356182

摘要： A dynamic latching arrangement with a conditional driver, a system, and a method reduce power consumption, increase operating speed, and reduce the number of discrete components. The conditional driver selectively impresses a signal on an internal node of the circuit such that when a control signal is asserted, a signal related to the clock signal is generated, but when the control signal is not asserted, a different signal related to the clock signal is generated.

摘要翻译： 具有条件驱动器，系统和方法的动态锁定装置降低功耗，提高操作速度，并减少分立元件的数量。 条件驱动器选择性地在电路的内部节点上施加信号，使得当控制信号被断言时，产生与时钟信号相关的信号，但是当控制信号不被断言时，与时钟信号相关的不同信号 被生成。