公开(公告)号：US08536853B2

公开(公告)日：2013-09-17

申请号：US13601351

申请日：2012-08-31

申请人： D.C. Sessions

发明人： D.C. Sessions

IPC分类号： G05F3/16

CPC分类号： G05F1/575 ,  G05F3/24

摘要： An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

摘要翻译： 集成电路器件具有初级电压调节器和超低功率次级电压调节器。 当集成电路设备处于低功率睡眠模式时，超低功率二次电压调节器向用于提供数据保持和动态操作的某些电路（例如实时时钟和日历（RTCC））提供电压。 当集成电路处于工作模式时，主电压调节器为这些相同的某些电路提供电源。

公开(公告)号：US20100315056A1

公开(公告)日：2010-12-16

申请号：US12780471

申请日：2010-05-14

申请人： D.C. Sessions

发明人： D.C. Sessions

IPC分类号： G05F1/10

CPC分类号： G05F1/575 ,  G05F3/24

摘要： An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

摘要翻译： 集成电路器件具有初级电压调节器和超低功率次级电压调节器。 当集成电路设备处于低功率睡眠模式时，超低功率二次电压调节器向用于提供数据保持和动态操作的某些电路（例如实时时钟和日历（RTCC））提供电压。 当集成电路处于工作模式时，主电压调节器为这些相同的某些电路提供电源。

公开(公告)号：US20100121988A1

公开(公告)日：2010-05-13

申请号：US12564493

申请日：2009-09-22

申请人： Gregg Lahti ,  Rodney Pesavento ,  Joseph W. Triece ,  D.C. Sessions

发明人： Gregg Lahti ,  Rodney Pesavento ,  Joseph W. Triece ,  D.C. Sessions

IPC分类号： G06F3/00

CPC分类号： G06F13/124 ,  G06F13/28 ,  Y02D10/14

摘要： A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

摘要翻译： 微控制器或集成系统具有总线，与总线耦合的多个外围设备，非易失性存储器和与非易失性存储器耦合的状态机，并且可操作以通过读取初始化信息来初始化外围设备 从非易失性存储器写入外围设备。

公开(公告)号：US20080258812A1

公开(公告)日：2008-10-23

申请号：US11587103

申请日：2005-04-19

申请人： Elie G. Khoury ,  D.C. Sessions

发明人： Elie G. Khoury ,  D.C. Sessions

IPC分类号： H03F3/26

CPC分类号： H03F3/265 ,  H03F3/3061 ,  H03F3/45237 ,  H03F3/45704 ,  H03F2203/45401

摘要： A novel high-speed differential receiver (100) is disclosed that provides a new method and apparatus receiving and amplifying a small differential voltage with a rail-to-rail common mode voltage. The receiver output signals are differential signals with low skew and high symmetry. This high-speed differential receiver (100) is based on a common mode voltage normalization, which is based on a differential phase splitting methodology, before the resulting signal is recombined, normalized and amplified. The method involves using a differential signal splitting stage (110) followed by a common mode voltage normalization stage (130), then a controlled gain transimpedance amplification stage (150), and then amplification using one or two rail to rail amplification stages (170) that are symmetrical and balanced in nature.

摘要翻译： 公开了一种新颖的高速差动接收器（100），其提供了一种以轨至轨共模电压接收和放大小差分电压的新方法和装置。 接收机输出信号是具有低偏移和高对称性的差分信号。 该高速差分接收器（100）基于基于差分相位分割方法的共模电压归一化，在所得信号被重组，归一化和放大之前。 该方法包括使用差分信号分离级（110），随后是共模电压归一化级（130），然后使用受控增益跨阻抗放大级（150），然后使用一个或两个轨到轨放大级（170）进行放大， 本质上是对称和平衡的。

公开(公告)号：US07724087B2

公开(公告)日：2010-05-25

申请号：US11587103

申请日：2005-04-19

申请人： Elie G. Khoury ,  D.C. Sessions

发明人： Elie G. Khoury ,  D.C. Sessions

IPC分类号： H03F3/26

CPC分类号： H03F3/265 ,  H03F3/3061 ,  H03F3/45237 ,  H03F3/45704 ,  H03F2203/45401

摘要： A novel high-speed differential receiver is disclosed that provides a new method and apparatus receiving and amplifying a small differential voltage with a rail-to-rail common mode voltage. The receiver output signals are differential signals with low skew and high symmetry. This high-speed differential receiver is based on a common mode voltage normalization, which is based on a differential phase splitting methodology, before the resulting signal is recombined, normalized and amplified. The method involves using a differential signal splitting followed by a common mode voltage normalization stage, then a controlled gain transimpedance amplification, and then amplification using one or two rail to rail amplification stages that are symmetrical and balanced in nature.

摘要翻译： 公开了一种新颖的高速差动接收器，其提供了一种以轨至轨共模电压接收和放大小差分电压的新方法和装置。 接收机输出信号是具有低偏移和高对称性的差分信号。 该高速差分接收器基于在模拟信号被重组，归一化和放大之前基于差分相位分离方法的共模电压归一化。 该方法包括使用差分信号分离，随后进行共模电压归一化阶段，然后进行受控增益互阻放大，然后使用一个或两个本质上对称和平衡的轨至轨放大级进行放大。

公开(公告)号：US20100001889A1

公开(公告)日：2010-01-07

申请号：US12165950

申请日：2008-07-01

申请人： James E. Bartling ,  David L. Otten ,  D.C. Sessions

发明人： James E. Bartling ,  David L. Otten ,  D.C. Sessions

IPC分类号： H03M1/66 ,  H03M1/00

CPC分类号： H03M1/68 ,  H03M1/742 ,  H03M1/82

摘要： A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2n+m. In addition, a plurality of sample and hold circuits may be utilized for maintaining a plurality of analog output voltages.

摘要翻译： 高分辨率数模转换器包括可编程n位电流数模转换器（IDAC），m位可编程计数器/定时器，将随时间充电的电容器的IDAC恒定电流转换为 精密（高分辨率）模拟电压，以及用于存储精密模拟电压的采样和保持电路。 来自IDAC的恒定电流在由可编程计数器/定时器确定的时间周期内被施加到积分器，然后采样和保持电路将对电容器的最终电压进行采样并将其存储为模拟电压。 该高分辨率数/模转换器的模拟电压分辨率为n + m位或二进制2n + m。 此外，可以使用多个采样和保持电路来保持多个模拟输出电压。

公开(公告)号：US06348882B1

公开(公告)日：2002-02-19

申请号：US09625084

申请日：2000-07-25

申请人： John Charles Ciccone ,  D.C. Sessions ,  Carl Liepold

发明人： John Charles Ciccone ,  D.C. Sessions ,  Carl Liepold

IPC分类号： H03M520

CPC分类号： H04L25/0292 ,  H03M7/00 ,  H03M7/06 ,  H04L25/0274

摘要： A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.

摘要翻译： 提供信号转换器，用于将多电平编码的数字信号转换为二进制等效信号。 信号转换器包括参考电压发生器，多个四输入差分比较器，定时恢复电路和信号转换电路。 参考电压发生器用于产生多个逐渐变大的差分参考电压。 多个差分比较器各自用于将差分输入电压的幅度与逐渐变大的差分参考电压中的专用差分输入电压的幅度进行比较，并且如果差分输入电压的幅度更大则产生具有第一逻辑检测的差分输出电压 如果差分输入电压的幅度小于差分参考电压的幅度，则具有第二逻辑检测​​。 每个比较器具有偏移输入电压。 定时恢复电路被配置为从每个差分比较器接收差分输出电压，并且可操作以经由边沿检测导出时钟并产生恢复的时钟信号。 信号转换电路与定时恢复电路和差分比较器耦合，并且可操作地将差分输出电压转换为二进制等效。 还提供了一种方法。

公开(公告)号：US20120326694A1

公开(公告)日：2012-12-27

申请号：US13601351

申请日：2012-08-31

申请人： D.C. Sessions

发明人： D.C. Sessions

IPC分类号： G05F3/02

CPC分类号： G05F1/575 ,  G05F3/24

摘要： An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

摘要翻译： 集成电路器件具有初级电压调节器和超低功率次级电压调节器。 当集成电路设备处于低功率睡眠模式时，超低功率二次电压调节器向用于提供数据保持和动态操作的某些电路（例如实时时钟和日历（RTCC））提供电压。 当集成电路处于工作模式时，主电压调节器为这些相同的某些电路提供电源。

公开(公告)号：US20110050341A1

公开(公告)日：2011-03-03

申请号：US11578890

申请日：2005-04-19

申请人： Elie G. Khoury ,  D.C. Sessions

发明人： Elie G. Khoury ,  D.C. Sessions

IPC分类号： H03F3/45

CPC分类号： H03F3/265 ,  H03F3/3061 ,  H03F3/45237 ,  H03F2203/45166 ,  H03F2203/45221 ,  H03F2203/45611 ,  H03F2203/45666

摘要： A novel high-speed phase splitter circuit (100) and method of operation are disclosed. This high-speed phase splitter (100) creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit (100) uses a phase splitting input stage (110, 130) followed by several amplification stages (150, 170) that are symmetrical and balanced in nature.

摘要翻译： 公开了一种新颖的高速相分离器电路（100）和操作方法。 该高速分相器（100）从单端输入信号产生差分轨至轨输出信号，具有固有的低偏移和对称输出。 电路（100）使用相分离输入级（110,130），随后是几个在本质上是对称和平衡的放大级（150,170）。