公开(公告)号：US09201415B2

公开(公告)日：2015-12-01

申请号：US13341682

申请日：2011-12-30

申请人： Yong Ju Kim ,  Dae Han Kwon ,  Hae Rang Choi ,  Jae Min Jang

发明人： Yong Ju Kim ,  Dae Han Kwon ,  Hae Rang Choi ,  Jae Min Jang

IPC分类号： H03K19/00 ,  G05B19/042

CPC分类号： G05B19/042 ,  G05B2219/23314 ,  G05B2219/24036 ,  G05B2219/24037

摘要： An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.

摘要翻译： 内部控制信号调节电路包括：编程测试单元，被配置为响应于外部控制信号检测内部控制信号，并产生选择信号，测试代码和编程使能信号; 以及代码处理单元，被配置为响应于所述选择信号接收所述测试代码或编程代码并调节所述内部控制信号。

公开(公告)号：US08664987B2

公开(公告)日：2014-03-04

申请号：US13607234

申请日：2012-09-07

申请人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

IPC分类号： H03K5/00

CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/235

摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

摘要翻译： 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为对输入信号进行滤波并生成滤波的 信号与操作时钟同步。

公开(公告)号：US20130216017A1

公开(公告)日：2013-08-22

申请号：US13620564

申请日：2012-09-14

申请人： Dae-Han KWON ,  Yong-Ju Kim ,  JAE-IL Kim ,  Taek-Sang Song

发明人： Dae-Han KWON ,  Yong-Ju Kim ,  JAE-IL Kim ,  Taek-Sang Song

IPC分类号： H03K21/00

CPC分类号： H03K21/38 ,  H03K21/023

摘要： A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

公开(公告)号：US20130135038A1

公开(公告)日：2013-05-30

申请号：US13611298

申请日：2012-09-12

申请人： Ki Han KIM ,  Hyun Woo LEE ,  Dae Han KWON ,  Chul Woo KIM ,  Soo Bin LIM

发明人： Ki Han KIM ,  Hyun Woo LEE ,  Dae Han KWON ,  Chul Woo KIM ,  Soo Bin LIM

IPC分类号： G05F1/10

CPC分类号： H03K19/094 ,  H03K19/0013 ,  H03K19/09482

摘要： A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.

摘要翻译： 一种半导体装置，包括电源改变单元。 电源改变单元被配置为接收使能信号和电源电压，根据使能信号产生第一电压或第二电压，根据电平信号改变第二电压的电压电平，并且提供第一电压或 第二电压作为内部电路的驱动电压，其中内部电路接收第一输入信号以输出第二输入信号。

公开(公告)号：US20130099838A1

公开(公告)日：2013-04-25

申请号：US13334241

申请日：2011-12-22

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H03L7/095

CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

公开(公告)号：US08283962B2

公开(公告)日：2012-10-09

申请号：US12005515

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/00

CPC分类号： G06F1/06

摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US08130890B2

公开(公告)日：2012-03-06

申请号：US12005492

申请日：2007-12-27

申请人： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H04L7/02 ,  H04L7/04

CPC分类号： G11C29/02 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

摘要： A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

摘要翻译： 数据时钟分频器电路包括训练解码器和分频器。 响应于模式寄存器组的命令和地址，训练解码器输出表示时钟对准训练的开始的时钟对准训练信号。 响应于训练解码器的输出复位的分频器接收内部数据时钟以将内部数据时钟的频率分成两半。 数据时钟分频器电路确保足够的操作余量，使得数据时钟和系统时钟在预设的时钟训练操作时间内对齐，通过复位数据时钟以对应于时钟训练操作开始的定时，由此 为高速系统提供时钟训练。

公开(公告)号：US08130034B2

公开(公告)日：2012-03-06

申请号：US12833154

申请日：2010-07-09

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03F3/45

CPC分类号： H03F3/45192

摘要： A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

摘要翻译： 轨到轨放大器包括：NMOS型放大单元，被配置为对差分输入信号的DC电平高于第一阈值的区域中的差分输入信号进行放大操作，PMOS型折叠共源共栅放大 被配置为对差分输入信号的DC电平低于高于第一阈值的第二阈值的区域中的差分输入信号进行放大操作的单元，PMOS型折叠共源共栅放大单元是 级联耦合到NMOS型放大单元，以及自适应偏置单元，被配置为在差分输入信号的DC电平高于第二阈值的区域中断PMOS型折叠共源共栅放大单元的电流路径 响应于差分输入信号。

公开(公告)号：US20110140768A1

公开(公告)日：2011-06-16

申请号：US12647875

申请日：2009-12-28

申请人： Taek-Sang SONG ,  Dae-Han KWON ,  Jun-Woo LEE

发明人： Taek-Sang SONG ,  Dae-Han KWON ,  Jun-Woo LEE

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.

摘要翻译： 内部电压发生器包括：检测单元，被配置为与参考电压相比检测内部电压的电平; 第一驱动单元，被配置为响应于所述检测单元的输出信号，对输出所述内部电压的内部电压端子进行放电; 电流检测单元，被配置为检测流过所述第一驱动单元的放电电流; 以及第二驱动单元，其被配置为响应于所述电流检测单元的输出信号对所述内部电压端子进行充电。

公开(公告)号：US07952438B2

公开(公告)日：2011-05-31

申请号：US12217049

申请日：2008-06-30

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03B27/01

CPC分类号： H03L7/0812 ,  H03L7/18 ,  H03L7/24

摘要： An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

摘要翻译： 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。